Chapter 4: Parameter Settings
4–11
Power Management
November 2012
Altera Corporation
Arria V GZ Hard IP for PCI Express
Power Management
describes the Power Management parameter registers.
PHY Characteristics
lists the PHY characteristics.
Table 4–11. Power Management Parameters
Parameter
Value
Description
Endpoint L0s
acceptable latency
Maximum of 64 ns
Maximum of 128 n
Maximum of 256 ns
Maximum of 512 ns
Maximum of 1 us
Maximum of 2 us
Maximum of 4 us
No limit
This design parameter specifies the maximum acceptable latency that the
device can tolerate to exit the L0s state for any links between the device and
the root complex. It sets the read-only value of the Endpoint L0s acceptable
latency field of the
Device Capabilities Register
(
.
The Arria V GZ Hard IP for PCI Express and Avalon-MM Arria V GZ Hard IP
for PCI Express do not support the L0s or L1 states. However, in a switched
system there may be links connected to switches that have L0s and L1
enabled. This parameter is set to allow system configuration software to
read the acceptable latencies for all devices in the system and the exit
latencies for each link to determine which links can enable Active State
Power Management (ASPM). This setting is disabled for Root Ports.
The default value of this parameter is 64 ns. This is the safest setting for
most designs.
Endpoint L1
acceptable latency
Maximum of 1 us
Maximum of 2 us
Maximum of 4 us
Maximum of 8 us
Maximum of 16 us
Maximum of 32 us
No limit
This value indicates the acceptable latency that an Endpoint can withstand
in the transition from the L1 to L0 state. It is an indirect measure of the
Endpoint’s internal buffering. It sets the read-only value of the Endpoint L1
acceptable latency field of the
Device Capabilities Register
.
The Arria V GZ Hard IP for PCI Express and Avalon-MM Arria V GZ Hard IP
for PCI Express do not support the L0s or L1 states. However, in a switched
system there may be links connected to switches that have L0s and L1
enabled. This parameter is set to allow system configuration software to
read the acceptable latencies for all devices in the system and the exit
latencies for each link to determine which links can enable Active State
Power Management (ASPM). This setting is disabled for Root Ports.
The default value of this parameter is 1 µs. This is the safest setting for
most designs.
Table 4–12. PHY Characteristics
Parameter
Value
Description
Gen2 transmit
deemphasis
3.5dB
6dB
Specifies the transmit deemphasis for Gen2.Altera recommends the
following settings:
■
3.5dB: Short PCB traces
■
6.0dB: Long PCB traces.
Use ATX PLL
On/Off
When enabled, the Hard IP for PCI Express uses the ATX PLL instead of the
CMU PLL. For other configurations, using the ATX PLL instead of the CMU
PLL reduces the number of transceiver channels that are necessary. This
option requires the use of the soft reset controller and does not support the
CvP flow. For more information about channel placement, refer to