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2–6
Chapter 2: Board Components
Featured Device: Arria II GX Device
Arria II GX FPGA Development Board Reference Manual
February 2011
Altera Corporation
Table 2–4
lists the I/O count for the EP2AGX125 and EP2AGX260 device.
Table 2–5
lists the Arria II GX device pin count and usage by function on the
development board.
Migration Support
Although the target FPGA for this development board is the EP2AGX125EF35 device,
the first device released in this 40nm FPGA family, the board supports migration to
the largest Arria II GX device, the EP2AGX260EF35.
Table 2–6
describes the features of the Arria II GX EP2AGX260EF35 device.
Table 2–4. I/O Count for the EP2AGX125 and EP2AGX260 Device
Package
Device
Bank
Total
(1)
3A
3B
4A
4B
5A
5B
6A
6B
7A
7B
8A
8B
1152-pin Flip Chip
FBGA
EP2AGX125 70
—
74
16
66
—
66
—
70
16
74
—
452
EP2AGX260 70
32
74
32
66
32
66
32
70
32
74
32
612
Note to
Table 2–4
:
(1) Transceiver signals are not included.
Table 2–5. Arria II GX Device Pin Count and Usage
Function
I/O Standard
I/O Count
Special Pins
DDR3 ×16 Port
1.5-V SSTL
49
2 Diff ×8 DQS
DDR2 SODIMM ×64 Port
1.8-V SSTL
120
8 Diff ×8 DQS
MAX Bus
1.5-V CMOS
8
—
Flash, SRAM, FSM Bus
2.5-V CMOS
82
—
PCI Express ×8
2.5-V CMOS + XCVR
41
1 REFCLK, 8 XCVR
HSMC Port A
2.5-V CMOS + LVDS + XCVR
104
4 XCVR, 17 LVDS, 5 Clock Inputs
HSMC Port B
(1)
2.5-V CMOS + XCVR
102
4 XCVR, 1 Clock Input
Gigabit Ethernet
2.5-V CMOS + LVDS
16
1 Clock Input
Buttons
1.8-V + 2.5-V CMOS
3
1 DEV_CLRn
Switches
2.5-V CMOS
4
—
LCD
2.5-V CMOS
11
—
LEDs
2.5-V CMOS
7/9
(1)
—
Clocks or Oscillators
2.5-V CMOS + LVDS + LVPECL
13/15
(1)
5 REFCLK
Device I/O Total:
458/564
(1)
Note to
Table 2–5
:
(1) The HSMC port B is populated when the board uses an EP2AGX260 device. To support the HSMC port B, there are two additional LEDs and a
REFCLK in quadrant 3.
Table 2–6. Arria II GX Device EP2AGX260EF35 Features
ALMs
Equivalent
LEs
M9K RAM
Blocks
Total RAM
Kbits
18-bit × 18-bit
Multipliers
PLLs
Transceivers
Package Type
102,600
256,500
950
11,756
736
6
16
1152-pin FBGA
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