AL5068S Designer’s Guide
No. AL5068S-E00-105
Altec Electronic AG
Seite 3 / 25
TABLE OF CONTENTS
1.
INTRODUCTION................................................................................................. 5
1.1 Overview ...................................................................................................... 5
1.2 Product
description....................................................................................... 5
1.3 Features ....................................................................................................... 6
1.4
Command Sets and S-Registers .................................................................. 6
2.
TECHNICAL OVERVIEW ................................................................................... 7
2.1 Dialing procedures ....................................................................................... 7
2.2 AT
Commands ............................................................................................. 7
2.2.1 Configuration Commands ......................................................................... 7
2.2.2 AT Connection Commands....................................................................... 7
2.3 ISDN
Protocols:............................................................................................ 8
2.4 Firmware
Updates ........................................................................................ 8
2.5 Supported Interfaces .................................................................................... 8
2.7 Power
consumption
and power down modes............................................... 9
2.8
Command Sets and S-Registers .................................................................. 9
3.
HARDWARE INTERFACE................................................................................ 10
3.1 Interface
Signals......................................................................................... 10
3.2 Signal
Descriptions..................................................................................... 10
3.3 S
0
INTERFACE .......................................................................................... 16
3.4 External
Reset Interface............................................................................. 17
3.4.1 Recommended Reset Circuit .................................................................. 17
3.5 IOM-2
Bus
Interface ................................................................................... 18
4.
DESIGN CONSIDERATIONS ........................................................................... 19
4.1 PC
Board
Layout Guidelines ...................................................................... 19
4.1.1 General................................................................................................... 19
4.1.2 Electromagnetic Interference (EMI) Considerations ............................... 20
4.1.3 Other Considerations.............................................................................. 20
4.2 Manufacturing
Considerations.................................................................... 21
5.
PACKAGE DIMENSIONS................................................................................. 22
6.
SOCKET MODEM APPROVALS ..................................................................... 23
6.1 Considerations
for
Telecom Approvals....................................................... 23
6.1.1 ISDN Connection .................................................................................... 23
6.2 Considerations
for
Electrical Safety............................................................ 23
6.2.1 Conditions for Maintaining Safety Compliance. ...................................... 23
6.2.2 Power Supply [EN60950-1:2001, 1.6]..................................................... 23
6.3 Considerations for EMC ............................................................................. 24
6.3.1 EMC Compliance (EU Countries) ........................................................... 24
6.3.2 Installation in Host Systems (European Countries)................................ 24
7.
Appendix A ...................................................................................................... 25
7.1
Schematic of external codecs .................................................................... 25
