FMC-CAMERALINK User Manual
V2.7 - 5th February 2019
5.1.4 Base/Medium/Full Output Configuration
The following tables show the pin usage for emulating a Base/Medium or Full camera from an FPGA design.
Signal Name
Direction
FMC pin
SDR pin (Con. 1)
xclk_p
out
LA_N_18*
18
xclk_n
out
LA_P_18*
5
x_p<0>
out
LA_P_21
15
x_n<0>
out
LA_N_21
2
x_p<1>
out
LA_N_20*
16
x_n<1>
out
LA_P_20*
3
x_p<2>
out
LA_P_19
17
x_n<2>
out
LA_N_19
4
x_p<3>
out
LA_N_14*
19
x_n<3>
out
LA_P_14*
6
cc_p<1>
in
LA_N_00*
22
cc_n<1>
in
LA_P_00*
9
cc_p<2>
in
LA_P_04
10
cc_n<2>
in
LA_N_04
23
cc_p<3>
in
LA_N_03*
24
cc_n<3>
in
LA_P_03*
11
cc_p<4>
in
LA_P_02
12
cc_n<4>
in
LA_N_02
25
ser_tfg_p
out
LA_N_05*
21
ser_tfg_n
out
LA_P_05*
8
ser_tc_p
in
LA_N_15*
7
ser_tc_n
in
LA_P_15*
20
Table 8 : Camera Link Connector 1 (Base/Medium/Full Output Configuration)
Page 11
Pin-out
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