Alpha Data ADM-XRC-7Z2, Руководство пользователя

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ADM-XRC-7Z2 User Manual
V1.2 - 24th Feb 2020
4.5.4 REFCLK200M
The fixed 200MHz reference clock, REFCLK200M, is a differential clock signal using LVDS. Three
phase-matched copies are distributed to Global Clock inputs on the Zynq PL.
This clock can be used to generate application-specific clock frequencies using the PLLs within the Virtex-6
FPGA. It is also suitable as the reference clock for the IO delay control block (IDELAYCTRL) and memory
interfaces.
Signal Target FPGA Input IO Standard "P" pin "N" pin
REFCLK200M_A IO_L13_MRCCC_10 LVDS_25 AG17 AG16
REFCLK200M_B IO_L12_MRCC_33 SSTL15 G5 G4
REFCLK200M_C IO_L13_MRCC_33 SSTL15 F5 E5
Table 11 : REFCLK200M Connections
4.5.5 PS_CLK33M3
The Zynq PS is provided with a 33.333MHz reference clock at the PS_CLK input on pin A22. This clock is
asynchronous to the clocks generated by the Si5338B.
Signal Target FPGA Input IO Standard "P" pin "N" pin
PS_CLK33M3 PS_CLK_500 LVCMOS18 A22 -
Table 12 : PS_CLK33M3 Connections
4.5.6 USB_REFCLK24M
The USB PHY and hub are provided with a 24.0MHz reference clock. This clock is asynchronous to the clocks
generated by the Si5338B and is not connected to the Zynq SoC.
4.5.7 ETH_CLK25M
The Ethernet PHYs are provided with 25.0MHz reference clocks generated by the Si5338B. These are not
connected to the Zynq SoC.
4.5.8 ETH1_CLK125M
The Ethernet PHY 1 generates a 125MHz reference clock that is connected to the Zynq PL at pin AF14.
Signal Target FPGA Input IO Standard "P" pin "N" pin
ETH1_CLK125M IO_L12_MRCC_10 LVCMOS25 AF14 -
Table 13 : ETH1_CLK125M Connections
4.5.9 BU_REFCLK40M
The BU-67301 and Zynq PL are provided with a 40.0MHz reference clock. It is connected to the PL on
clock-capable pin AE28. This clock is asynchronous to the clocks generated by the Si5338B.
Page 11 Functional Description
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