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ADM-VPX3-9V2 User Manual

3.5 PCI Express

The ADM-VPX3-9V2 is capable of PCIe Gen 3 between 1 and 16 lanes. The FPGA drives these lanes dirctly

using the Integrated PCI Express block from Xilinx. Negotiation of PCIe link speed and number of lanes used is

generally automatic and does not require user intervention.

PCI Express reset (PERST#) dedicated reset pin on the FPGA (IO_T3U_N12_PERSTN0_65) is driven by either/

or VPX system reset or the slot maskable reset.

Complete Pinout Table

signal PERSTN0.

The other pin assignments for the high speed lanes are provided in the pinout attached to the

Complete Pinout

Table

The PCI Express specification requires that all add-in cards be ready for enumeration within 120ms after power

is valid (100ms after power is valid + 20ms after PERST is released). The ADM-VPX3-9V2 does not meet this

requirement, but will configure in about 200ms when configured from a tandem bitstream with the proper SPI

constraints detailed in the llink:section:Configuration From Flash Memory. For more details on tandem

configuration, see Xilinx XAPP 1179.

Note:

Different SBCs/backplanes will benefit from different RX equalization schemes within the PCIe IP core

provided by Xilinx. Alpha Data recommends using the following setting if a user experiences link errors or

training issues with their system: within the IP core generator, change the mode to "Advanced" and open the

"GT Settings" tab, change the "form factor driven insertion loss adjustment" from "Add-in Card" to

"Chip-to-Chip" (See Xilinx PG195, PG213, and PG239 for more details).

Page 15

Functional Description
ad-ug-1377_v1_2.pdf

Содержание ADM-VPX3-9V2

Страница 1: ...ADM VPX3 9V2 User Manual Document Revision 1 2 13th October 2020...

Страница 2: ...hout prior written consent from Alpha Data Parallel Systems Ltd Head Office Address Suite L4A 160 Dundee Street Edinburgh EH11 1DQ UK Telephone 44 131 558 2600 Fax 44 131 558 2700 email sales alpha da...

Страница 3: ...10 3 3 VPX P1 and P2 11 3 3 1 Differential Pairs 11 3 3 2 P1 GDISC1 11 3 3 3 VBAT 11 3 3 4 SYSCON 11 3 3 5 MP01 11 3 3 6 AX_RESETL 11 3 3 7 MSKRST 11 3 3 8 P2 GPIO 12 3 3 9 MP02 12 3 4 Clocking 13 3 4...

Страница 4: ...lete Pinout Table 23 List of Figures Figure 1 ADM VPX3 9V2 Product Photo 1 Figure 2 ADM VPX3 9V2 Top View 3 Figure 3 Thermal Performance 5 Figure 4 ADM VPX3 9V2 VU9P Block Diagram 6 Figure 5 ADM VPX3...

Страница 5: ...ction thermal management configuration 3U 4HP VPX form factor Four banks of DDR4 SDRAM 72 bit wide memory ECC 16GB 4GB per bank rated at 2666MT s All 32 wafers of P1 and P2 are capable of 28 Gpbs oper...

Страница 6: ...2F4F2U 14 2 11 SLT3 PAY 1F2U 14 2 12 SLT3 PAY 3F2U 14 2 13 SLT3 PAY 2U2U 14 2 17 SLT3 PER 2F 14 3 1 SLT3 PER 1F 14 3 2 SLT3 PER 1U 14 3 3 SLT3 PER 1Q 14 3 4 SLT3 SWH 6F6U 14 4 1 SLT3 SWH 8F 14 4 2 SLT...

Страница 7: ...ies with 4HP pitch slot profiles from AV48 1 and AV48 2 respectively Description Measure Total Dy 100 mm PCB Dy 94 mm Total Dx 171 mm PCB Dx 160 mm Total Dz 21 5 mm Weight no heat sink 180g Table 1 Me...

Страница 8: ...wer rails are unused and unconnected Power consumption estimation requires the use of the Xilinx XPE spreadsheet and a power estimator tool available from Alpha Data Please contact support alpha data...

Страница 9: ...ing the Alpha Data power estimator in conjunction with the Xilinx Power Estimator XPE downloadable at http www xilinx com products technology power xpe html Download the UltraScale tool and set the de...

Страница 10: ...TAG programing header micro usb access to system montior and factory programing headers GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO 4GB DDR4 2666 72 bits 5x 16 bit BGA 4GB DDR4 2666 72 bits 5x 16 bit BGA...

Страница 11: ...5x 16 bit BGA AVR uC PWR Reg 0 VS1 VS2 P0 VS3 VS3 SM2 3 SM0 1 JTAG JTAG JT AG GA GA REF AUX AUX R N P1 GD1 VBAT MSKR SYSC 232TD 232RD P2 JTAG 232TD GPIO 232RD GPIO RSVD RSVD FireFly B04 Fat Pipe Fat P...

Страница 12: ...DBG_USER_IN_0 1 Net DBG_USER_IN_0 0 SW1 2 OFF Service Mode System Monitor normal operation System Monitor Service Mode firmware update etc SW1 3 OFF CLK_SEL Board synchronizes to onboard 25MHz Board...

Страница 13: ...8 Front Panel LEDs Comp Ref Function Net Name ON State OFF State D8 USER_LED_0_1V8 User defined 0 User defined 1 D7 USER_LED_1_1V8 User defined 0 User defined 1 D6 USER_LED_2_1V8 User defined 0 User...

Страница 14: ...t can provide an external reference timing pulse or clock By default this clock is forwarded as net name AUXCLK_SE_1V8 GPIO in FPGA bank 64 The net AUXCLK_DIR_1V8 when driven high will change the exte...

Страница 15: ...s an optional bidirectional open drain IO pin defined in the VPX specification at P1 pin G1 It is controlled at the FPGA by net GDiscrete1_OUT and GDiscrete1_IN both of which have external pull ups An...

Страница 16: ...external pull down Nets P2_GPIO_ _1V8 are the input output pins to send and receive data MP02 at P1 pins G1 and G3 can be used as a serial 3 3V UART interface as per OpenVPX when configured with the a...

Страница 17: ...n the FPGA All clock names in the section below can be found in Complete Pinout Table FABRIC_CLK 300MHz IO Bank 66 25MHz 30ppm Source Si5338 Clock Synth AUXCLK_SE_1V8 BANK 64 0 1 2 3 AUXCLK_DIR_1V8 BA...

Страница 18: ...the section USB Interface The PROGCLK_0 connects at each usable MGT quad at the MGTREFCLK0 location Quad 224 is the only exception which is connected to VPX REFCLK instead PROGCLK0_9 is connected to...

Страница 19: ...n within 120ms after power is valid 100ms after power is valid 20ms after PERST is released The ADM VPX3 9V2 does not meet this requirement but will configure in about 200ms when configured from a tan...

Страница 20: ...Data to pre fit industrial or commercial optical FireFly modules Please contact sales alpha data com for full details and options FireFly optical modules are robust to mechanical shock up to 11 ms 20...

Страница 21: ...m the Xilinx Memory Interface Generator MIG tool An example memory exerciser project is included in the ADM VPX3 9V2 SDK All constraint information is included in Complete Pinout Table The 8Gb compone...

Страница 22: ...ard input supply from PCIE edge 3V3_DIG ADC03 3 3V generated onboard for QSFP optics 2V5_DIG ADC04 2 5V generated onboard for DRAM 2V5_CLK ADC05 2 5V generated onboard for clock circuitry 1V8_DIG ADC0...

Страница 23: ...dby Powered off Flashing Green Flashing Red together Attention critical alarm active Flashing Green Flashing Red alternating Service Mode Flashing Green Red Attention alarm active Red Missing applicat...

Страница 24: ...bitstream which should be visible to the operating system using e g Windows Device Manager or lspci in Linux in order to provided confidence that the card is working correctly when installed in a syst...

Страница 25: ...format MCS size 256 interface SPIx4 loadbit up 0x0000000 directory to file filename bit 0th location Program with vivado hardware manager with these settings see xapp1233 SPI part mt25qu02g spi x1_x2_...

Страница 26: ...HU4IGT4A The address pins A2 A1 and A0 are all strapped to a logical 0 Write protect WP Serial Clock SCL and Serial Data SDA pin assignments can be found in Complete Pinout Table with the names SPARE_...

Страница 27: ...11_GC_61 1 2 BB31 DDR4_0_A12 IO_L8N_T1L_N3_AD5N_40 IO_L8N_T1L_N3_AD5N_61 1 2 AW31 DDR4_0_A13 IO_L14N_T2L_N3_GC_40 IO_L14N_T2L_N3_GC_61 1 2 AR31 DDR4_0_A14 IO_L19N_T3L_N1_DBC _AD9N_40 IO_L19N_T3L_N1_DB...

Страница 28: ...IO_L7P_T1L_N0_QBC_ AD13P_62 1 2 AA32 DDR4_0_DM5 IO_L19P_T3L_N0_DBC _AD9P_42 IO_L19P_T3L_N0_DBC _AD9P_63 1 2 AE31 DDR4_0_DM6 IO_L13P_T2L_N0_GC_ QBC_42 IO_L13P_T2L_N0_GC_ QBC_63 1 2 AH34 DDR4_0_DM7 IO_L...

Страница 29: ...IO_L15P_T2L_N4_AD11P_41 IO_L15P_T2L_N4_AD11P_62 1 2 BD36 DDR4_0_DQ32 IO_L9P_T1L_N4_AD12P_41 IO_L9P_T1L_N4_AD12P_62 1 2 BC36 DDR4_0_DQ33 IO_L11N_T1U_N9_GC_41 IO_L11N_T1U_N9_GC_62 1 2 BE36 DDR4_0_DQ34...

Страница 30: ...DR4_0_DQ6 IO_L5N_T0U_N9_AD14N_40 IO_L5N_T0U_N9_AD14N_61 1 2 AG31 DDR4_0_DQ60 IO_L11P_T1U_N8_GC_42 IO_L11P_T1U_N8_GC_63 1 2 AJ33 DDR4_0_DQ61 IO_L8N_T1L_N3_AD5N_42 IO_L8N_T1L_N3_AD5N_63 1 2 AF32 DDR4_0_...

Страница 31: ...IO_L10P_T1U_N6_QBC _AD4P_62 1 2 Y31 DDR4_0_DQS5_C IO_L22N_T3U_N7_DBC _AD0N_42 IO_L22N_T3U_N7_DBC _AD0N_63 1 2 W31 DDR4_0_DQS5_T IO_L22P_T3U_N6_DBC _AD0P_42 IO_L22P_T3U_N6_DBC _AD0P_63 1 2 AD31 DDR4_0...

Страница 32: ...1_A15 IO_L17N_T2U_N9_AD1 0N_D15_65 IO_L17N_T2U_N9_AD1 0N_D15_65 1 2 BC28 DDR4_1_A2 IO_T1U_N12_SMBALERT_65 IO_T1U_N12_SMBALERT_65 1 2 AY25 DDR4_1_A3 IO_L10N_T1U_N7_QBC _AD4N_A13_D29_65 IO_L10N_T1U_N7_Q...

Страница 33: ...L1P_T0L_N0_DBC_ RS0_65 1 2 AN18 DDR4_1_DM3 IO_L19P_T3L_N0_DBC _AD9P_66 IO_L19P_T3L_N0_DBC _AD9P_66 1 2 BF14 DDR4_1_DM4 IO_L1P_T0L_N0_DBC_67 IO_L1P_T0L_N0_DBC_67 1 2 BA12 DDR4_1_DM5 IO_L7P_T1L_N0_QBC_...

Страница 34: ...T3L_N2_AD1P_66 1 2 AM20 DDR4_1_DQ28 IO_L24N_T3U_N11_66 IO_L24N_T3U_N11_66 1 2 AN16 DDR4_1_DQ29 IO_L21N_T3L_N5_AD8N_66 IO_L21N_T3L_N5_AD8N_66 1 2 BD18 DDR4_1_DQ3 IO_L3P_T0L_N4_AD15P_66 IO_L3P_T0L_N4_AD...

Страница 35: ...U_N11_AD 2N_67 IO_L18N_T2U_N11_AD 2N_67 1 2 AP14 DDR4_1_DQ56 IO_L20N_T3L_N3_AD1N_67 IO_L20N_T3L_N3_AD1N_67 1 2 AL14 DDR4_1_DQ57 IO_L24P_T3U_N10_67 IO_L24P_T3U_N10_67 1 2 AN13 DDR4_1_DQ58 IO_L21N_T3L_N...

Страница 36: ..._A24_65 IO_L4P_T0U_N6_DBC_ AD7P_A24_65 1 2 AM17 DDR4_1_DQS3_C IO_L22N_T3U_N7_DBC _AD0N_66 IO_L22N_T3U_N7_DBC _AD0N_66 1 2 AL17 DDR4_1_DQS3_T IO_L22P_T3U_N6_DBC _AD0P_66 IO_L22P_T3U_N6_DBC _AD0P_66 1 2...

Страница 37: ...D1N_48 IO_L20N_T3L_N3_AD1N_71 1 2 A30 DDR4_2_A13 IO_L24N_T3U_N11_48 IO_L24N_T3U_N11_71 1 2 M27 DDR4_2_A14 IO_L9P_T1L_N4_AD12P_48 IO_L9P_T1L_N4_AD12P_71 1 2 L27 DDR4_2_A15 IO_L9N_T1L_N5_AD12N_48 IO_L9N...

Страница 38: ...DR4_2_DM4 IO_L19P_T3L_N0_DBC _AD9P_46 IO_L19P_T3L_N0_DBC _AD9P_69 1 2 E40 DDR4_2_DM5 IO_L7P_T1L_N0_QBC_ AD13P_47 IO_L7P_T1L_N0_QBC_ AD13P_70 1 2 M31 DDR4_2_DM6 IO_L13P_T2L_N0_GC_ QBC_46 IO_L13P_T2L_N0...

Страница 39: ...IO_L23P_T3U_N8_47 IO_L23P_T3U_N8_70 1 2 C34 DDR4_2_DQ31 IO_L20N_T3L_N3_AD1N_47 IO_L20N_T3L_N3_AD1N_70 1 2 F33 DDR4_2_DQ32 IO_L24P_T3U_N10_46 IO_L24P_T3U_N10_69 1 2 G31 DDR4_2_DQ33 IO_L20N_T3L_N3_AD1N...

Страница 40: ...P_46 IO_L5P_T0U_N8_AD14P_69 1 2 G34 DDR4_2_DQ6 IO_L5N_T0U_N9_AD14N_47 IO_L5N_T0U_N9_AD14N_70 1 2 R33 DDR4_2_DQ60 IO_L2N_T0L_N3_46 IO_L2N_T0L_N3_69 1 2 U31 DDR4_2_DQ61 IO_L5N_T0U_N9_AD14N_46 IO_L5N_T0U...

Страница 41: ...U_N6_DBC _AD0P_69 1 2 A39 DDR4_2_DQS5_C IO_L10N_T1U_N7_QBC _AD4N_47 IO_L10N_T1U_N7_QBC _AD4N_70 1 2 B39 DDR4_2_DQS5_T IO_L10P_T1U_N6_QBC _AD4P_47 IO_L10P_T1U_N6_QBC _AD4P_70 1 2 J30 DDR4_2_DQS6_C IO_L...

Страница 42: ...C_72 IO_L14N_T2L_N3_GC_74 1 2 H24 DDR4_3_A5 IO_L12N_T1U_N11_GC_72 IO_L12N_T1U_N11_GC_74 1 2 J24 DDR4_3_A6 IO_L12P_T1U_N10_GC_72 IO_L12P_T1U_N10_GC_74 1 2 K23 DDR4_3_A7 IO_L9N_T1L_N5_AD12N_72 IO_L9N_T1...

Страница 43: ...O_L20P_T3L_N2_AD1P_73 1 2 J20 DDR4_3_DQ10 IO_L12P_T1U_N10_GC_71 IO_L12P_T1U_N10_GC_73 1 2 J19 DDR4_3_DQ11 IO_L12N_T1U_N11_GC_71 IO_L12N_T1U_N11_GC_73 1 2 L20 DDR4_3_DQ12 IO_L9P_T1L_N4_AD12P_71 IO_L9P_...

Страница 44: ..._DQ37 IO_L15N_T2L_N5_AD11N_71 IO_L15N_T2L_N5_AD11N_73 1 2 G20 DDR4_3_DQ38 IO_L14P_T2L_N2_GC_71 IO_L14P_T2L_N2_GC_73 1 2 G19 DDR4_3_DQ39 IO_L14N_T2L_N3_GC_71 IO_L14N_T2L_N3_GC_73 1 2 B20 DDR4_3_DQ4 IO_...

Страница 45: ...O_L5P_T0U_N8_AD14P_70 IO_L5P_T0U_N8_AD14P_72 1 2 P14 DDR4_3_DQ67 IO_L2P_T0L_N2_70 IO_L2P_T0L_N2_72 1 2 M16 DDR4_3_DQ68 IO_L6N_T0U_N11_AD6N_70 IO_L6N_T0U_N11_AD6N_72 1 2 P15 DDR4_3_DQ69 IO_L3N_T0L_N5_A...

Страница 46: ...S8_C IO_L4N_T0U_N7_DBC_ AD7N_70 IO_L4N_T0U_N7_DBC_ AD7N_72 1 2 R16 DDR4_3_DQS8_T IO_L4P_T0U_N6_DBC_ AD7P_70 IO_L4P_T0U_N6_DBC_ AD7P_72 1 2 H23 DDR4_3_ODT IO_L11N_T1U_N9_GC_72 IO_L11N_T1U_N9_GC_74 1 2...

Страница 47: ...6 B15 MGT AC45 FIREFLY_0_RX2_P MGTYRXP2_124 MGTYRXP2_128 J6 B14 MGT AB44 FIREFLY_0_RX3_N MGTYRXN3_124 MGTYRXN3_128 J6 A15 MGT AB43 FIREFLY_0_RX3_P MGTYRXP3_124 MGTYRXP3_128 J6 A14 MGT BE8 FIREFLY_0_SC...

Страница 48: ...B3 MGT W41 FIREFLY_1_TX2_N MGTYTXN2_125 MGTYTXN2_129 J15 A5 MGT W40 FIREFLY_1_TX2_P MGTYTXP2_125 MGTYTXP2_129 J15 A6 MGT V39 FIREFLY_1_TX3_N MGTYTXN3_125 MGTYTXN3_129 J15 B5 MGT V38 FIREFLY_1_TX3_P M...

Страница 49: ...1_FPGA_SCL IO_L8P_T1L_N2_AD5P_68 IO_L8P_T1L_N2_AD5P_68 P0 G4 1 8 LVCMOS18 BB10 IPMB1_FPGA_SDA IO_L8N_T1L_N3_AD5N_68 IO_L8N_T1L_N3_AD5N_68 P0 F4 1 8 LVCMOS18 BC8 NVMRO_FPGA IO_L9P_T1L_N4_AD12P_68 IO_L9...

Страница 50: ...N1_229 P2 F2 MGT Y7 P2_1_TX_PIN_P MGTYTXP1_229 MGTYTXP1_229 P2 E2 MGT L3 P2_10_RX_PIN_N MGTYRXN2_231 MGTYRXN2_231 P2 B11 MGT L4 P2_10_RX_PIN_P MGTYRXP2_231 MGTYRXP2_231 P2 A11 MGT L8 P2_10_TX_PIN_N MG...

Страница 51: ...P0_230 MGTYRXP0_230 P2 A5 MGT U8 P2_4_TX_PIN_N MGTYTXN0_230 MGTYTXN0_230 P2 E5 MGT U9 P2_4_TX_PIN_P MGTYTXP0_230 MGTYTXP0_230 P2 D5 MGT T1 P2_5_RX_PIN_N MGTYRXN1_230 MGTYRXN1_230 P2 C6 MGT T2 P2_5_RX_...

Страница 52: ...N_T3L_N5_AD8N_64 1 8 LVCMOS18 BF22 P2_GPIO_G5_1V8 IO_L4N_T0U_N7_DBC_ AD7N_64 IO_L4N_T0U_N7_DBC_ AD7N_64 P2 G5 1 8 LVCMOS18 AL24 P2_GPIO_G5_DIR IO_L22P_T3U_N6_DBC _AD0P_64 IO_L22P_T3U_N6_DBC _AD0P_64 1...

Страница 53: ...PCIE_TX5_PIN_N MGTYTXN1_225 MGTYTXN1_225 P1 F6 MGT AT7 PCIE_TX5_PIN_P MGTYTXP1_225 MGTYTXP1_225 P1 E6 MGT AR8 PCIE_TX6_PIN_N MGTYTXN2_225 MGTYTXN2_225 P1 E7 MGT AR9 PCIE_TX6_PIN_P MGTYTXP2_225 MGTYTX...

Страница 54: ...RM_ADV BB9 PROGCLK0_9_P IO_L11P_T1U_N8_GC_68 IO_L11P_T1U_N8_GC_68 1 8 LVDS with DIFF_TERM_ADV AA37 PROGCLK1_0_PI N_N MGTREFCLK1N_125 MGTREFCLK1N_129 MGT REFCLK AA36 PROGCLK1_0_PIN_P MGTREFCLK1P_125 MG...

Страница 55: ...N_T2L_N1_GC_ QBC_61 1 2 AW29 REFCLK300M_0_ PIN_P IO_L13P_T2L_N0_GC_ QBC_40 IO_L13P_T2L_N0_GC_ QBC_61 1 2 AW26 REFCLK300M_1_ PIN_N IO_L13N_T2L_N1_GC_ QBC_A07_D23_65 IO_L13N_T2L_N1_GC_ QBC_A07_D23_65 1...

Страница 56: ...23 UART_0_TX_1V8 IO_L20N_T3L_N3_AD1N_64 IO_L20N_T3L_N3_AD1N_64 P1 G9 1 8 LVCMOS18 BA20 USER_LED_0_1V8 IO_L7P_T1L_N0_QBC_ AD13P_64 IO_L7P_T1L_N0_QBC_ AD13P_64 1 8 LVCMOS18 BB20 USER_LED_1_1V8 IO_L7N_T1...

Страница 57: ...flicker when unconstrained or FPGA is unconfigured 7 Oct 2020 1 1 K Roth Corrected bank arrows on block diagrams in section Functional Description added note about clamshell for DDR4 SDRAM added vibr...

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