Allen-Bradley POINT I/O 1734-VHSC24, Руководство пользователя, Страница: 32 / 64

Publication 1734-UM003A-EN-P - August 2000
3-4 Very High Speed Counter Module Input and Output Data
EEPROM Fault status bit (EF) - If a fault is detected with the
EEPROM during power up tests, this bit is asserted to 1. It indicates
that the content of the EEPROM has been corrupted, most likely
caused by loss of power during an executing write.
Not Ready status bit (NR) - Whenever power is applied to the
module, the hardware must be initialized. During this time, the NR bit
will be asserted and the
green module status indicator will flash .
Output Fault Status indicators (FS) - where bit 11 is output 1 and
bit 10 is output 0. A 1 indicates the output is either shorted or open.
Output Status indicators (OS) - where bit 9 is output 1 and bit 8 is
output 0. A 1 indicates the output is ON, 0 it is OFF.
Z input Status (ZS) - This bit indicates the present status of the Z
input (1 indicates Z is ON, 0 indicates Z is OFF). This bit is unaffected
by Z Invert, ZI, in the Counter Configuration word.
B input Status (BS) - This bit indicates the present status of the B
input (1 indicates B is ON, 0 indicates B is OFF).
A input Status (AS) - This bit indicates the present status of the A
input (1 indicates A is ON, 0 indicates A is OFF).
C[1,0] Stored data count - This count cycles through [ 0 0 ], [ 0 1 ], [ 1
0 ], [ 1 1 ], [ 0 0 ]
…
Each time the stored/accumulated count words are
updated, C[1,0] is incremented. This feature assumes the host’s sample
rate (including network delay and program scan) is as fast or faster
than the frequency of the event which updates C[1,0].
Zero frequency Detected (ZD) - This bit is operational when
frequency configurations are programmed (configurations: period/rate
[5], continuous/rate [6], rate measurement [7])
.
In period/rate [5] and continuous/rate [6] configurations,
counts are acquired during the ON state of the Z input. At very
low frequencies the counter saturates, indicating a zero
frequency detect. The time it takes to determine a zero
frequency in these two configurations can be as long as 6.7
seconds ( 16,777,216 counts x 1/5MHz x 2 half cycles of Z ).
In rate measurement [7] configuration pulses on the A input
are counted over a sample interval specified by the time base.
The time it takes to determine a zero frequency in this
configuration will be determined by the sample interval (ex:
time base = 0.300 second
∴
300 milliseconds to determine ZF).