ZYNQ Ultr FPGA Board AXU2CGA/B User Manual
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Part 12: PCIE Interface
There is a PCIE x1 slot on the AXU2CGA/B board for connecting PCIE
peripherals, and the PCIE communication speed is up to 5Gbps. PCIE signal is
directly connected to LANE0 of BANK505 PS MGT transceiver. The schematic
diagram of PCIE x 1 design is shown in Figure 12-1:
Figure 12-1: PCIE Schematic
PCIE Interface ZYNQ Pin Assignment
Signal Name
Pin Name
Pin
Number
Description
PCIE_TXP
PS_MGTTXP0_505
E25
PCIE Data Transmission Positive
PCIE_TXN
PS_MGTTXN0_505
E26
PCIE Data Transmission Negative
PCIE_RXP
PS_MGTRXP0_505
F27
PCIE Data Receive Positive
PCIE_RXN
PS_MGTRXN0_505
F28
PCIE Data Receive Negative
PCIE_REFCLK_P
PS_MGTREFCLK0P_505
F23
PCIE Data Reference Clock Positive
PCIE_REFCLK_N
PS_MGTREFCLK0N_505
F24
PCIE Data Reference Clock Negative
