5
2. Power Amplifier Circuit
The transmitted signal is oscillated by the VCO, amplified by the drive amplifier
(IC112) and younger amplifier (Q115), and input to the final power module
(IC110). The signal is then amplified by the final power module (IC110) and led
to the antenna switch (D110) and low-pass filter (L113, L114, L115, L116,
C215, C216, C202, C203 and C204), where unwanted high harmonic waves
are reduced as needed, and the resulting signal is supplied to the antenna.
3. APC Circuit
Part of the transmission power from the low-pass filter is detected by D111 and
D112, converted to DC. The detection voltage is passed through the APC circuit
(Q118, Q117, Q116), then it controls the APC voltage supplied to the younger
amplifier Q115 and the final power module IC110 to fix the transmission power.
3) PLL Synthesizer Circuit (DR-135)
1. PLL
The dividing ratio is obtained by sending data from the CPU (IC1) to pin 2 and
sending clock pulses to pin 3 of the PLL IC (IC116). The oscillated signal from
the VCO is amplified by the buffer (Q134 and Q135) and input to pin 15 of
IC116. Each programmable divider in IC116 divides the frequency of the input
signal by N according to the frequency data, to generate a comparison frequency of
5 or 6.25 kHz.
2. Reference Frequency Circuit
The reference frequency appropriate for the channel steps is obtained by dividing
the 21.25 MHz reference oscillation (X103) by 4250 or 3400, according to the data
from the CPU (IC1). When the resulting frequency is 5 kHz, channel steps of 5,
10, 15, 20, 25, 30, and 50 kHz are used. When it is 6.25 kHz, the 12.5 kHz
channel step is used.
3. Phase Comparator Circuit
The PLL (IC116) uses the reference frequency, 5 or 6.25kHz. The phase
comparator in the IC116 compares the phase of the frequency from the VCO
with that of the comparison frequency, 5 or 6.25kHz, which is obtained by the
internal divider in IC116.
4. PLL Loop Filter Circuit
If a phase difference is found in the phase comparison between the reference
frequency and VCO output frequency, the charge pump output (pin 13) of IC116
generates a pulse signal, which is converted to DC voltage by the PLL loop
filter and input to the varicap of the VCO unit for oscillation frequency control.
Содержание DR-135
Страница 14: ...14 12 M3826M8L269GP XA0818 CPU Terminal Connection TOP VIEW 269 ...
Страница 23: ...23 11 M57788M XA0077 ...
Страница 31: ...31 3 LCD Assembly FF0017 NUT UE0035 FM0034 FG0305 CPU BOARD ST0064 EL0049 TL0024 DG0037 TL0023 NUT ST0068 ...
Страница 59: ...59 3 MAIN Unit Side A DR 135 UP 0400B 4 MAIN Unit Side B DR 135 UP 0400B ...
Страница 61: ...61 7 MAIN Unit Side A DR 435 UP 0415 VCO Unit Side A VCO Unit Side B 8 MAIN Unit Side B DR 435 UP 0415 ...
Страница 62: ...62 9 TNC Unit Side A UP 0402 DR 135TP only OPTION unit EJ41U 10 TNC Unit Side B UP 0402 DR 135TP only ...
Страница 65: ...65 3 MAIN Unit DR 235 TO CN6 OPTION CN7 TO CPU CN2 TO CPU CN1 TO OPTION Downloaded by RadioAmateur EU ...
Страница 67: ...67 5 TNC Unit DR 135TP only or option CN6 CN7 TO MAIN CN107 ...
Страница 68: ...68 BLOCK DIAGRAM 1 DR 135 ...
Страница 69: ...69 2 DR 235 Downloaded by RadioAmateur EU ...
Страница 70: ...70 3 DR 435 ...