PX845EV1/ PX845EV1 PRO
32
DRAM RAS# Precharge
This item allows you to select the DRAM RAS# precharge time. The ROW address strobe
must precharge again before DRAM is refreshed. An inadequate configuration may result in
incomplete data. Options: 3
、
2 and By SPD (default)
DRAM Data Integrity Mode
This item can let you choose the DRAM Integrity Mode depending on the type of DRAM
installed. Options: Non-ECC (default)
、
ECC
Refresh Mode Select
Select the refresh mode. Options: 15.6 us
、
7.8 us
、
64 us
、
Auto (default)
Dram Read Thermal Mgnt
This item allows you to enable/disable the DRAM Read Thermal Management function.
Options: Disabled (default)
、
Enabled
System BIOS Cacheable
When enabled, accesses to system BIOS ROM addressed at F0000H-FFFFFH are cached,
provided that the cache controller is enabled. Options: Enabled (default), Disabled
Video BIOS Cacheable
Select “Enabled” to allow caching of the video BIOS which may improve performance. If
any other program writes to this memory area, a system error may result.
Options: Enabled, Disabled (default)
Memory Hole at 15M-16M
When enabled, you can reserve an area of system memory for ISA adapter ROM. When this
area is reserved, it cannot be cached. Refer to the user documentation of the peripheral you
are installing for more information. Options: Disabled (default)
、
Enabled
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transaction cycles.
Select “Enabled” to support compliance with PCI specifications.
Options: Disabled, Enabled (default)
Delay Prior to Thermal
Select the delay time before thermal activation from high temperatures.
Options: 4 Min
、
8 Min
、
16 Min (default)
、
32 Min
