Akai LTA-26C904, Руководство по обслуживанию

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9
57 SCL IIC bus （ clock ）
58 SDA IIC bus
（
data
）
60 GPIO0 GPIO1 selection signal
59 GPIO1 GPIO2 selection signal
62 WR# CPU write signal
63 RD# CPU read signal
61 CS CPU chip selection signal （ low level effective ）
56 INTN Interrupt signal （ low level effective ）
84 ALE Address latch signal
86 RESET Reset signal (high level effective)
85 V5SF SF Power
（
+5V
）
4 DP_HS Line synchronization signal
5 DP_VS Field synchronization signal
23 DP_CLK Clock signal
6 DP_DE_FLD DE I/O terminal
64 ADDR0
┆ ┆
71 ADDR7
CPU address （ R0~R7 ） signal
83 A_D0
┆ ┆
76 A_D7
CPU address/data passage
MISC port control signal
162
CVBS_OUT2 SCART2 interface CVBS signal output
163 CVBS_OUT1 SCART1 interface CVBS signal output
157 TEST MODE Test mode signal (grounding)
158 AIN_HS Line synchronization signal
159 AIN_VS Field synchronization signal
205 XTALI
204 XTALO
Crystal oscillator interface
SDRM
控制端口
124 MA0
┆ ┆
121 MA3
118 MA4
┆ ┆
113 MA9
125 MA10
126 MA11
Memory address （ A0~A11 ）
156 DQM0
133 DQM1
109 DQM2
87 DQM3
Memory read/write byte signal
128 BA0 Memory stack address selection