Pin No.
Pin Name
I/O
Description
-71-
IC DESCRIPTION - 7/9 (HD6417034AF112) - 2/4
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
_____
WAIT
___
CS7
PA3
____
WRL
___
WR
PA4
_____
WRH
____
LBS
PA5
___
RD
PA6
_____
BACK
PA7
VSS
_____
BREQ
PA8
________
IRQOUT
___
AH
_______
ADTRG
PA9
DPL
TIOCA1
PA10
DPH
TIOCB1
PA11
_____
IRQ0
TCLKA
DACK0
PA12
_____
IRQ1
TCLKB
DREQ0
PA13
_____
IRQ2
DACK1
PA14
_____
IRQ3
DREQ1
PA15
VCC
I
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
–
I
I/O
O
I
I/O
I/O
I/O
I
O
I/O
I
I/O
I
O
I/O
I
I/O
–
Wait. Requests the insertion of wait states (TW) into the bus cycle when the external address
space is accessed.
Chip select 7. Chip select signals for accessing external memory and devices.
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Lower write. Indicates write access to the lower eight bits of an external device.
____
Write. Brought low during write access. (Also used as WRL.)
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Upper write. Indicates write access to the upper eight bits of an external device.
Upper/lower byte strobe. Upper and lower byte strobe signals. (Also used as WRH and A0.)
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Read. Indicates reading of data from an external device.
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Bus request acknowledge.
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Ground
Bus request. Driven low by an external device to request bus ownership.
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Slave interrupt request output.
Address hold. Address hold timing signal for a device using a multiplexed address/data bus.
A/D trigger input: External trigger input for starting A/D conversion.
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Lower data bus parity
ITU input capture/output compare (channel 1). Input capture or output compare pins.
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Upper data bus parity
ITU input capture/output compare (channel 1). Input capture or output compare pins.
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Interrupt request 0.
ITU timer clock input. External clock input pins for ITU counters.
DMA transfer acknowledge (channel 1). Indicates that DMA transfer is acknowledged.
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Interrupt request 1
ITU timer clock input. External clock input pins for ITU counters.
DMA transfer request (channel 0). Input pins for external DMA transfer requests.
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Interrupt request 2.
DMA transfer acknowledge (channels 0 and 1). Indicates that DMA transfer is acknowledged.
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Interrupt request 3.
DMA transfer request (channels 0 and 1). Input pins for external DMA transfer requests.
Port A. 16-bit input/output pins. Input or output can be selected individually for each bit.
Power.
