Aiwa XD-DV300, Руководство по обслуживанию

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9
IC BLOCK DIAGRAM
IC, PCM1723
IC, MC44724A
IC, MM1454XFBE
Data ROM
OSC
24 1 5
XTO XTI
MCKO
27 MHz
Counter N
Counter M
Internal System Clock
Phase Detector
&
Loop Filter
VCO
2
SCKO
256 fs / 384 fs
C/Fsync/VBI F/Vsync Hsync
Sync_generator
BG
CGMS,
WSS_gen CC_gen
DVdd
DVss
DVIA [7 : 0]
DVIB [7 : 0]
A/B_sel
TP
Clock
Chip A
Reset
PAL/NTSC
SO
SDA/SI
SCL/SCK
SEL
TEST
DA
Vss
DA
Vdd
Ibias 2
Vref 2
C/Cr/R 2
C/Cr/R 2
CVBS/Cb/B 2
CVBS/Cb/B 2
Y/G 2
Y/G 2
Ibias 1
Vref 1
C/Cr/R 1
C/Cr/R 1
CVBS/Cb/B 1
CVBS/Cb/B 1
Y/G 1
Y/G 1
C/Cr/R 1Vdd
CVBS/Cb/B 1Vdd
Y/G 1Vdd
Y/G 2Vdd C/Cr/R 2Vdd CVBS/Cb/B 2Vdd
TEST
I2C/SPI
Output Selector
BIAS
DAC
BIAS
DAC
DAC
DAC
DAC
DAC
0
0
0
0
0
0
0
0
0
0
H, V
Y
Demux
Cb
Cr
RGB Matrix
Modulator
Off_set
Copy
Protection
bus
bus
30
28
51
27
10 13
15
14
24
23
18
17
21
20
11
12
8
7
2
1
6
3
9
4
5
25
19 22 50 49 48
39
|
46
52
|
55
58
|
61
,
29
26
31
32
62
33 35 34 36
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
+
–
+
–
+
–
BIAS
VCC
RIN PNR B/Q DET QF6 ROUT LOUT GND
LIN VREF QF1 QF2 QF3 QF4 QF5
QSurround
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