Aiwa XD-DV300, Руководство по обслуживанию

Страница: 33 / 38

47
Pin No. Pin Name I/O Description
71
72
73, 74
75
76-78
79
80
81
82-84
85
86
87
88-91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108, 109
110
111
112
113, 114
115
116
117
118
119, 120
121
122
VDD
OSD_ACTIVE
PD_0, 1
VSS
PD_2-4
VDD
NC
VSS
PD_5-7
VSS
BLANK
CREF
EXT_OSD_0-3
NC
VDD
ACLK_441
ACLK_48
ACLK_32
VSS
CD_BCLK
CD_LRCLK
CD_ACLK
CD_ASDATA
SPDIF_IN
A_ACLK
VDD
BCLK
LRCLK
ASDATA
NC
VSS
SPDIF_OUT
AUDIO_SYNC
TM1, TM0
ZTEST
SCAN_TE
PREQ_N
VDD
SBD_15, 14
NC
SBD_13
I
O
O
I
O
I
—
I
O
I
O
O
I
O
I
I
I
I
I
I
I
I
I
I
O
I
O
O
O
O
I
O
O
I
I
I
O
I
I/O
—
I/O
Power (3.3V).
On screen display active.
Pixel data output bus 0, 1.
Ground.
Pixel data output bus 2-4.
Power (3.3V).
Not connected.
Ground.
Pixel data output bus 5-7.
Ground.
Blank (composite).
Chroma reference for pixel data.
External OSD palette selection bus 0-3.
Not connected.
Power (3.3V).
Audio input clock for 44.1kHz*N.
Audio input clock for 48kHz*N.
Audio input clock for 32kHz*N.
Ground.
CD-Serial DAC bit clock.
CD-Left right clock.
CD-External audio clock.
CD-Audio serial data line.
Sony/Philips data interface-input.
Output audio clock.
Power (3.3V).
Serial DAC bit clock.
Serial DAC left right clock.
Audio serial data line.
Not connected.
Ground.
Sony/Philips data interface output.
Audio sync strobe.
Test mode 1, 0.
Test mode pin.
Scan test mode pin.
PCM FIFO request.
Power (3.3V).
SDRAM data bus 15, 14.
Not connected.
SDRAM data bus 13.
All manuals and user guides at all-guides.com