Aiwa SX-DV1, Руководство по обслуживанию

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1 VBDPLL O Reference voltage.
2 PLLVSS – Ground pin for data PLL and related analog circuitry.
3 LPIO O The output of VCO integrator.
4 LPIN I The negative input terminal of VCO integrator.
5 LPFO O The output of loop filter amplifier.
6 LPFN I The negative input terminal of loop filter amplifier.
7 IREF I
Current reference input. It generate reference current for data PLL.
Connect an external resistor to this pin and PLLVSS.
Phase comparator output. Output the phase difference of EFM and Pck.
8 PDO O Sink or (source) a constant current to loop filter over this pin when phase difference occurs.
Otherwise, this pin is high impedance.
9 JITFO O The output terminal of RF jitter meter.
10 JITFN I The input terminal of RF jitter meter.
11 PLLVDD – Power for data PLL and related analog circuitry.
12 FOO O Focus servo output. PDM output of focus servo compensator.
13 TRO O Tracking servo output. PDM output of tracking servo compensator.
14 PWMOUT1 O 1st general PWM output. (Not used)
15 PWMOUT2 O 2nd general PWM output. (DPD mute control output)
16 DVDD – +5V digital supply.
17 DMO O Disk motor control output. PWM output.
18 FMO O Feed motor control. PWM output.
19 TROPENPWM O Tray open output. Controlled by
µ
P. (Not used)
20 FG I Motor hall sensor input. (Not used)
21 DVSS – Digital ground.
22 TRCLOSE O Tray close output. (Not used)
23 IO9/CS I/O
General programmable I/O (Standby) / Chip select signal for FLASH ROM selection
(when in IDE update FLASH ROM mode), active low (not used).
24 UALE I/O Address latch enable. (Connected to pull-up resistor)
25 ~ 28 UAD7 ~ UAD4 I/O
µ
P address/data bus.
29 DVSS – Digital ground.
30 ~ 33 UAD3 ~ UAD0 I/O
µ
P address/data bus.
34 DVDD3 – +3.3V digital supply.
35 UP2_7/UCS2 I/O
µ
P upper address bus /
µ
P chip select 2 (for internal RAM).
36 UP2_6/UCS1 I/O
µ
P upper address bus /
µ
P chip select 1 (for internal RAM).
37 ~ 42 UP2_5 ~ UP2_0 I/O
µ
P upper address bus.
43 DVSS – Digital ground.
44 ~ 51 UA7 ~ UA0 I/O
µ
P lower address bus.
52 DMVSS – Ground pin for DRAM clock circuitry.
53 DMVDD – Power pin for DRAM clock circuitry.
54 UA16 I/O
µ
P address bit 16/general programmable I/O.
55 UPSEN O Programmable store enable output.
Pin No. Pin Name I/O Description
IC DESCRIPTION -3/5 (IC, MT1388E -1/5) XD-DV1
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