Pin No.
Pin Name
I/O
Description
-56-
3.65 V ± 150 mV
Device address output
Ground
3.65 V ± 150 mV
Device address output
Ground
3.65 V ± 150 mV
Device address output
Reset input, active "L".
TDM transmit data.
ROM Select
RSEL
Selection
0
16-bit ROM
1
8-bit ROM
Ground
3.65 V ± 150 mV
TDM receive data
TDM clock input
TDM frame synch
TDM output enable, active "L".
Audio transmit frame sync
Select PLL1
Audio transmit serial data port
Select PLL0
SEL_PLL2
SEL_PLL0
Clock Output
0
0
2.5 x DCLK
0
1
3 x DCLK
1
0
3.5 x DCLK
1
1
4 x DCLK
Ground
3.65 V ± 150 mV
Select PLL2. See the table for pin number 33
No connect pins. Leave open.
Audio master clock for audio DAC
Audio transmit bit clock
S/PDIF (IEC958) Format Output
No connect pins. Leave open.
Ground
3.65 V ± 150 mV
Audio receive serial data
Audio receive frame synch
IC DESCRIPTION -7/9 (ES4318F) -1/4
–
O
–
–
O
–
–
O
I
O
I
–
–
I
I
I
O
O
I
O
I
I
O
–
–
–
I
I
1
2 ~ 7
8
9
10 ~ 16
17
18
19 ~ 23
24
25
26
27
28
29
30
31
32
33
41
42
43
44
45
46
VCC
LA4 ~ LA9
VSS
VCC
LA10 ~ LA16
VSS
VCC
LA17 ~ LA21
______
RESET
TDMDX
RSEL
VSS
VCC
TDMDR
TDMCLK
TDMFS
________
TDMTSC
TWS
SEL_PLL1
TSD
SEL_PLL0
SPDIF_DOBM
NC
VSS
VCC
RSD
RWS
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9
2
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9
8
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9
9
2
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9
4
2
9
8
0
5
1
5
1
3
6
7
3
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