Pin No.
Pin Name
I/O
Description
-50-
34
35
36
37
38
39
40
41
42
43
44
VCOM
VREFH
AVDD
AVSS
DZF1
MCLK
P/S
DIF0
CSN
DIF1
SCL/CCLK
LOOP0
SDA/CDTI
LOOP1
O
I
–
–
O
I
I
I
I
I
I/O
I
Common Voltage Output Pin, AVDD/2. Large external capacitor around 2.2µF is used to reduce
power-supply noise.
Positive Voltage Reference Input Pin, AVDD
Analog Power Supply Pin, 4.5 V -~ 5.5 V
Analog Ground Pin, 0V
Zero Input Detect 1 Pin (Note 2). When the input data of the group 1 follow total 8192 LRCK
cycles with "0" input data, this pin goes to "H".
Master Clock Input Pin
Parallel/Serial Select Pin. "L": Serial control mode, "H": Parallel control mode
Audio Data Interface Format 0 Pin in parallel control mode.
Chip Select Pin in 3-wire serial control mode. This pin should be connected to DVDD at I
2
C bus
control mode.
Audio Data Interface Format 1 Pin in parallel control mode.
Control Data Clock Pin in serial control mode. I
2
C = "L": CCLK (3-wire Serial), I
2
C = "H": SCL
(I
2
C Bus)
Loopback Mode 0 Pin in parallel control mode. Enables digital loop-back from ADC to 3 DACs.
Control Data Input Pin in serial control mode. I
2
C = "L": CDTI (3-wire Serial), I
2
C = "H": SDA
(I
2
C Bus)
Loopback Mode 1 Pin (Note 1). Enables all 3 DAC channels to be input from SDTI1.
Notes:
1. SDOS, SMUTE, DFS, and LOOP1 pins are ORed with register data if P/S = "L".
2. The group 1 and 2 can be selected by DZFM2-0 bits if P/S = "L" and DZFE = "L".
3. This pin becomes OVF pin if OVFE bit is set to "1" at serial control mode.
4. All input pins should not be left floating.
IC DESCRIPTION -2/9 (AK4527B-VQ) -2/2
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