Aiwa AZG-5, Руководство по обслуживанию

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26
Pin No. Pin Name I/O Description
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Terminal to which external crystal is connected for system clock oscillation 2.
Ready signal input for system control interface.
Serial data input for system control interface.
Serial data output for system control interface.
Serial clock output for system control interface.
Latch signal output for CXD2652 interface.
CXD2652 reset signal output.
Record data output enable. (Enabled at “H”.)
Circuit selection output for wide PLL. (Normal PLL at “H”.)
Connected to Vss.
Connected to VDD.
Connected to VDD.
Pull up.
Connected to Vss.
Connected to Vss.
Connected to Vss.
Connected to Vss.
Connected to Vss.
Temperature sensor signal input.
Connected to Vss.
Spindle FG signal input.
Pull up to VDD.
Pull up to VDD.
CXD2652 SENS signal input.
CXD2652 monitor signal input 3.
CXD2652 monitor signal input 2.
CXD2652 monitor signal input 1.
CXD2652 monitor signal input 0.
DRAM refresh selection signal output. (Microprocessor control at “H”. DSP at “L”.)
RAS signal output.
CAS signal output.
Not used.
PWM output for sled motor drive.
Not used.
DIGITAL-IN SUB-Q sync input.
CXD2652 status, sync input.
Serial data input for CXD2652 interface.
Serial data output for CXD2652 interface.
Serial clock output for CXD2652 interface.
SUB-Q/ADIP sync input.
Not used.
XTALI
ARDY
SIN
SOUT
ACLK
XLAT
XRST
TX
CLV
AVSS
AVREF
AVDD
VLEVEL
AN6
AN5
AN4
AN3
AN2
TEMP
AN0
SPFG
EXI0
TEST0
SENS
MON3
MON2
MON1
MON0
BUP
M_RAS
M_CAS
XLAT3
SEO
N.C.
DQSY
XINT
SRDT
SWDT
SCKO
SQSY
XLAT1
—
I
I
O
O
O
O
O
O
—
—
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
I
I
I
O
O
I
O