24
VP (CLV servo lock judgement) signal input.
Monitor 3 signal input from LC89641.
Monitor 2 signal input from LC89641.
Monitor 1 signal input from LC89641.
Monitor 0 signal input from LC89641.
DEFECT signal input.
PPIT signal input.
Outputs H during data read.
Direction input of sled movement (inner
™
outer at H, outer
™
inner at L).
LC89641 reset signal output.
Holder OPEN (H)/CLOSE (L) signal input and standby cancel.
Power supply control output of DRAM. (power of DRAM is turned on at L.)
PCK signal input from LC89641.
FSEQ signal input from LC89641.
Not used (L output).
Connected to GND.
Connected to VDD.
CAS signal output to DRAM.
RAS signal output to DRAM.
Control selector signal output (controlled by microprocessor at H) over DRAM
microprocessor control/DSP.
System power supply control (power ON at L).
Audio mute signal output (mute ON at H).
Serial data output to LCD remote control.
Standby signal output of headphones driver (standby at L).
HOLD signal input (HOLD ON at L).
Headphones jack insertion detection signal input (insert at L).
Domestic version/foreign version switching input (domestic version at H).
Test mode/main mode switching input (test mode at L).
I
I
I
I
I
I
I
O
I
O
I
O
I
I
O
—
—
O
O
O
O
O
O
O
I
I
I
I
VP
MON3
MON2
MON1
MON0
DEFECT
PPIT
READ
SEDIR
RESET
HOLDER
DRAMSW
PCK
FSEQ
NC
VSS3
VDD3
MCAS
MRAS
BUP
P-CONT
AMUTE
RMCDT
PWSTB
HOLD
PLG-I
JAPAN
TEST
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61-67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin No.
Pin Name
I/O
Description
Содержание AM-HX50
Страница 9: ...10 9 BLOCK DIAGRAM 7 27 EFMIN MOE MCAS MRAS MWE X200 16 93MHZ 72 S300 OPEN CLOSE P CONT ...
Страница 10: ...12 11 WIRING 1 MAIN 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H I J ...
Страница 11: ...14 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H I J ...
Страница 12: ...16 15 SCHEMATIC DIAGRAM ...
Страница 28: ...32 IC BLOCK DIAGRAM IC TA2131FL IC S 93C46AMFN IC TC7W74FU ...
Страница 32: ...931196 Printed in Singapore 2 11 IKENOHATA1 CHOME TAITO KU TOKYO 110 JAPAN TEL 03 3827 3111 ...