Revision B • 7/00
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4 Equipment Description
INPUT MODULE
For this section refer to the two Input Module
schematic pages (drawings 92-1004) and to the
two SIM schematic pages (drawings 92-1001 and
92-1002) in Chapter 6.
Analog SIM
The two identical balanced inputs (A and B)
connect directly to the SIM socket. With an Ana-
log SIM (99-1001) installed, the stereo audio sig-
nals are unbalanced and amplified by OP275 dual
differential opamps on the SIM card. Four single-
pole single-throw (SPST) solid-state analog
switches toggle between the two inputs according
to the faceplate A/B button selection.
The selected stereo input is then routed through
trimpots R59 and R60 (Trim R and Trim L). The
outputs of the trimpots go through buffer/ampli-
fier U4 before being converted into digital signals
by U5, a single chip ADC (Analog-to-Digital Con-
verter). The ADC chip output (SDATA_SIM) is
routed back to the Input PCA through the SIM
socket.
Digital SIM
With a Digital SIM installed (99-1002), the
AES/EBU input is coupled to an AES/EBU Re-
ceiver (U2) through an isolating transformer (T1)
and the A/B selection relay (K1).
U2 converts the incoming AES/EBU signal into
a serial data signal (SDATA) with a separate left/
right clock (FSYNC) and serial clock (SCLK). In
normal operation, the SDATA signal is routed
through an Asynchronous SRC (Sample Rate Con-
verter), U4, to synchronize the incoming digital
audio with the DSP (via the FS64 clock). The out-
put, SRC_DATA is then routed back to the Input
module through the SIM socket as SDATA.
The SRC can be bypassed by physically
jumpering E1 to E2. This switches which section
of U1 is active. Normally the odd pins couple the
signals through to the output while the even pins
are in a tri-state mode (at a high impedance). With
E1 jumpered to E2, the RX_SDATA from AES/
EBU receiver U2 is connected directly to the In-
put module via the even pins of U1, while the odd
pins are at a high impedance.
If valid digital audio is not received, or if there
are excessive errors (e.g., loss of lock, parity er-
rors, biphase encoding violation), an ERF (Error
Flag) signal is sent back to the Input module where
a NOR gate in U15 mutes the SDATA signal.
Input Module
Every Input module fader gets its reference volt-
ages (both High and Low) from the DSP. Each
fader’s wiper output connects via a separate line
to the DSP for individual channel level control.
The faceplate assignment switches (A/B select,
bus assignment, Cue, Off-Line) are all on a single
universal switch SIM. Each is a momentary SPST
switch with an integral LED indicator. The
switches connect directly to the gate array chip
(FPGA, U14) while the LEDs on the switches are
controlled by the FPGA through FET switches Q1
- Q4, Q13 and Q14.
The module’s On/Off switches mount on a sub-
assembly (PR&E # 95-969-1). Each switch is a
momentary SPST with incandescent lamps con-
trolled by the FPGA through FETs Q5 - Q12 and
Q15. The FETs not only turn the lamps on or off,
they also generate an AC-like voltage to increase
lamp life over normal DC powering.
When the Cue or Off-Line function is active, pre-
fader controlled audio is applied to the appropri-
ate summing bus. When any Program select but-
ton is active, fader-controlled audio for that chan-
nel is then connected to the selected digital Pro-
gram bus.
The ten-position Logic Settings DIP switch
(DS1) is used to tell the FPGA whether logic con-
trol is to be active on the A or B input along with
