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5. Structure of the ANET429
ANET429-x Users Manual 36
5.1 System FPGA
The System FPGA includes the ASP processor Interface logic, the Interface Logic for
the BIU processor and the ARINC429 Encoder / Decoder Logic.
The following features are implemented in the System FPGA:
Global RAM interface and arbitration
SPI controller for updating the on board SPI-Flashes
ARINC429 Encoder / Decoder
IRIG-B Logic
Time Code Processor Function
µMon-Software
Trigger-I/O Logic
Discrete-I/O Logic
ASP & BIU processor Interface
5.2 Global RAM
128MByte RAM, shared between the ASP-, BIU-Processor and the FPGA internal
Microcontroller.
5.3 BIU Section
The BIU consist of the BIU processor, the ARINC429 Encoder/Decoder logic to handle
up to 16 ARINC429 channels, the Trigger-Logic to handle the Trigger-I/O signals and a
SPI-Flash for BIU-Processor Boot, all implemented in the FPGA.
5.3.1 ARINC-429 Encoder
The encoder converts the parallel data into a serial ARINC429 encoded data stream
and appends the parity and the gap bits. The programmable frame times between two
labels can be set in the range from 0 up to 255 ARINC429 bits.
The encoder provides the following error injection capabilities:
Gap Error
(-1 bit)
Bitcount Error (+/- 1 bit)
Coding Error (fixed at bit position 12)
Parity Error (if no special transmission mode is chosen)