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Error register. A summary is reported in the Status Byte Register, as selected by two masking
registers – the Input Trip Enable register and the Standard Event Status Enable Register. Two
further mask registers, the Service Request Enable register and the Parallel Poll Response Enable
register, control operation of the GPIB hardware Service Request and Parallel Poll (and the
associated
ist
message) respectively. It is recommended that, when controlling the unit through any
interface other than GPIB, the controller program should simply read the primary status registers
directly.
The instrument specific Input Trip Registers record events related to the electrical function of the
multimeter and the user inputs applied.
The Standard Event Status Register, supported by the Execution Error and Query Error registers,
records events concerned with command parsing and execution, and the flow of commands,
queries and responses across the interface. These are mainly of use during software development,
as a production test procedure should never generate any of these errors.
15.1
Input Trip Registers (ITR & ITE).
The Input Trip Register reports electrical conditions that have arisen during the operation of the
multimeter. By its nature it is common to all interfaces. It reports events that have resulted in the unit
unexpectedly disabling the internal current source and reverting the primary measurement to Vdc.
The Input Trip Register has a summary bit in the Status Byte Register, with an associated Enable
Register to determine which, if any, bits contribute to that summary. All these registers are bit fields,
where each bit is independent (so more than one may be set simultaneously) and has the
significance detailed below.
15.1.1
Input Trip Register (ITR)
Bits 7-1
Not used, permanently 0.
Bit 0
Over Voltage Protect:
Set when an overvoltage is applied between the
HI
and
LO
terminals in the following modes – Ohms (4 wire and 2 wire), Diode, Continuity,
Capacitance and Temperature measurement.
The bits in the Input Trip register are set when the event they report occurs, and then remain set
until read by the ITR? query. After the Response Message is sent any bits reporting conditions that
no longer apply will be cleared; any bit reporting a condition that remains true will remain set.
The Input Trip Enable Register provides the mask between the Input Trip Register and the Status
Byte Register. If any bit becomes ‘1’ in both registers, then the INTR bit (bit 1) will be set in the
Status Byte Register. This enable register is set by the ITE
<NRF>
command to a value 0 - 255, and
read back by the ITE? query (which will always return the value last set by the controller). On
power-up the ITE register is set to 0 and ITR is cleared (but bits it contains may be set after
initialisation in the unusual case of any of the conditions reported being true).
15.2
Standard Event Status Registers (ESR and ESE)
The Standard Event Status Register is defined by the IEEE Std. 488.2 GPIB standard. It is a bit
field, where each bit is independent and has the following significance:
Bit 7
Power On.
Set once the instrument is fully initialised and operating after either
power up from the application of mains, or when the
[Operate]
key is pressed in
standby. It is also set when first powered up on batteries although this is only useful
on USB as all other remote interfaces are not available under battery power.
Bits 6, 3 & 1:
Not used, permanently 0.
Bit 5
Command Error.
Set when a syntax error is detected in a command or parameter.
The parser is reset and parsing continues at the next byte in the input stream.
Bit 4
Execution Error.
Set when a non-zero value is written to the Execution Error
register, if a syntactically correct command cannot be executed for any reason.
Bit 2
Query Error.
Set when a query error occurs, because the controller has not issued
commands and read response messages in the correct sequence.
Bit 0
Operation Complete.
Set in response to the ‘*OPC’ command.
