AGP PM-V06, Руководство пользователя

Страница: 40 / 62

V06
This selection allows you to configure the system based on the specific features of the
installed chipset. This chipset manages bus speeds add access to system memory resources, such
as DRAM and the external cache. If also coordinates communications between the conventional
ISA bus and the PCI bus. It must be stated that these items should never need to be altered. The
default settings have been chosen because they provide the best operating conditions for your
system. The only time you might consider making any change would be if you discovered that
data was being lost while using your system.
3-9 DRAM Settings
The first chipset settings deal with CPU access to dynamic random access memory (DRAM).
The default timing have been carefully chose and should only be altered if data is being lost. Such
a scenario might well occur if your system had mixed speed DRAM chips installed so that greater
delays may be required to preserve the integrity of the data held in the slower memory chips.
3-9.1 DRAM Clock
The default value for this item is Host Clk.
Host Clk DRAM Clock equals to host (system clock).
HCLK-33M DRAM Clock equals to host clock minus 33Mhz.
3-9.2 SDRAM Cycle Length
The item allows you to select the value for SDRAM Cycle delay time. The
default value is 3ns.
The selections are: 2ns and 3ns.
3-9.3 Bank Interleave
The choice: Disabled, Enabled.
3-9.4 Memory Hole 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it can not be cached. The user information of peripherals that need to use this areas of
system memory usually discussed their memory requirement.
The choice: Enabled, Disabled.