Agilent Technologies E1437A, Руководство пользователя, Страница: 135 / 214

Comments:
For more details on the interaction among source, master and sync with multiple
modules and multiple mainframes see Managing multiple modules.
The master, multisync, source, and dsp parameters are interdependent with
legitimate combinations being as follows (along withthe resultant DSP clock rates):
MASTER SYNC SOURCE DSP
DSP CLOCK
RATE
N/A OFF 20.x (internal) N/A Internal source
N/A OFF EXT ADC External source
N/A OFF EXT OSC 20.48
N/A OFF EXT:PLL N/A 20
OFF

BUFFER FRONT N/A ADC Master ADC
OFF

BUFFER
FRONT N/A OSC 20.48
OFF REAR N/A ADC Master ADC
OFF REAR N/A OSC 20.48
ON FRONT 20.x N/A Source
ON FRONT EXT ADC External
ON FRONT EXT OSC 20.48
ON FRONT EXT:PLL N/A 20
ON REAR 20.x N/A Source
ON REAR EXT ADC External
ON REAR EXT OSC 20.48
ON REAR EXT:PLL N/A 20
BUFFER REAR N/A ADC Master ADC
BUFFER REAR N/A OSC 20.48
If fs >20,480,000 then dsp must = ADC
Th e maximum rate at wh ich data may be transferred to memory is determined by
the DSP clock rate: Max bytes/s. = 4 * DSP clock rate. In continuous mode the
maximum rate is limited to (4 * DSP clock rate)/2. However, you may successfully
perform this type of measurement by adding a level of decimation to reduce the
sample rate.
Example: The correct method to set up a synchronous multi-module group that insures that
all modules share the same ADC clock is:
! First, insure that one module is putting its clock on the backplane
OUTPUT <addrMaster>;" CLOCK:Master
1"
! Put each module into multi-sync mode with internal clock! (unless external
clock is connected to
! master HP E1437
through Ext Clk TTL connector).
! For each module address (except master):
OUTPUT <addrAll>;"Clock:Setup 2,0,1,0,20480000"
Reset State:
multisync =OFF, source =20480000, dsp =ADC, master =OFF, fs =20480000
See Also: FILTER:SETUP, DATA:SETUP
E1437A CLOCK:SETUP
ASCII Overview and Commands command/query
5-12
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