Agilent Technologies 8564EC, Руководство по обслуживанию

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Chapter 7 361
General Troubleshooting
Block Diagram Description
ADC
The spectrum analyzer can digitize signals with either the main ADC
on the A3 interface assembly, or the optional A16 fast ADC
(Option 007). The main ADC is used for digitizing video signals (when
the sweep time is
≥
30 ms) and various other signals such as PLL error
voltages. The fast ADC is used only to digitize video signals for sweep
times
≤
30 ms.
Main ADC (part of A3 interface assembly) For slower sweep
times (
≤
30 ms) the spectrum analyzer uses a successive-approximation
type of ADC. The main ADC has a 10-bit resolution but it is realized
with 12-bit hardware. The ADC algorithmic state machine (ADC ASM)
controls the interface between the start/stop control and the ADC itself,
switching between positive and negative peak detectors when the
NORMAL detector mode is selected, and switching the ramp counter
into the ADC for comparison to the analog sweep ramp.
Fast ADC When Option 007 is installed and sweep times
≤
30 ms are
selected, the spectrum analyzer digitizes video signals with the A16
fast ADC. The fast ADC uses an 8-bit flash ADC, sampled at a 12 MHz
rate. Only POS PEAK, NEG PEAK, and SAMPLE detector modes are
available with fast ADC; NORMAL detector mode is not available.
Pretriggering is possible with fast ADC.
Log Expand/Video Functions
The A3 interface assembly performs log expand and offset functions.
The log expand/log offset amplifier provides a 2 dB/Div log scale. When
the main ADC is used, the 5 dB/Div scale is derived by multiplying the
digitized 10 dB/Div trace data by two in the CPU. When the fast ADC is
used, the 5 dB/Div scale is derived by amplifying the video signal by
two. The 1 dB/Div scale is similarly derived by either multiplying the
2 dB/Div trace data by two (main ADC) or amplifying the video signal
by two (fast ADC).
The spectrum analyzer uses two types of video filters. An RC low-pass
circuit provides 300 Hz to 3 MHz video bandwidths. Video bandwidths
≤
100 Hz are generated using digital filtering. Digitally filtered video
bandwidths use a sample detector. When sample detection is selected,
the effective video bandwidth is limited to approximately 450 kHz.
When a digital filter is selected, a
D
appears along the left edge of the
CRT, indicating that something other than the normal detector mode is
being used.
After filtering, the video is sent to the positive and negative peak
detectors. These detectors are designed for optimum pulse response.
The positive peak detector resets at the end of each horizontal "bucket"
(there are 601 such buckets across the screen). The negative peak
detector resets at the end of every other bucket. When reset, the output
of the peak detector equals its input.