DM482e User Manual
AEMULUS
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3.1.5 MIPI
DM482e contains MIPI controller to communicate with MIPI (Mobile Industry Processor
Interface) RFFE (RF Front End) devices. It is capable of performing register 0 write, register
write, extended register write, extended register write long, register read, extended register
read as well as extended register read long operations. This feature avoids the hassle of
constructing MIPI SCLK and SDATA using vectors or patterns.
The MIPI RFFE Specification defines an interface between RFFE-capable devices, with one
master device and up to 15 slaves on a single RFFE bus. The RFFE Interface and bus structure is
illustrated below.
Figure 11: RFFE Interface and Bus Structure
MIPI uses two signal lines, a clock signal (SCLK) controlled by the master, a
unidirectional/bidirectional data signal (SDATA), and an I/O supply/reference voltage (VIO).
The choice of SDATA attribute is based on whether a slave device is write-only, or whether it
supports read/write capability.
