３７
Table 6
:
PCI Express Insertion Loss Budget, 1.25 GHz with Carrier Board Slot Card
Segment
Loss (dB)
max. Length
[mm/inches]
Notes
L
A
130/5.15
Allowance for 5.15 inches of module trace
3.45 dB loss
@ 0.28 dB / GHz
/ inch and 1.66 dB crosstalk allowance. Coupling caps not included.
Coupling
Caps
1.19 dB loss.
From PCI Express Card Electromechanical Spec., Rev.
1.1, parameters (L
ST
– L
SR
). Includes crosstalk allowance of 0.79 dB.
L
B
COM Express
TM
connector at 1.25 GHz measured value:
0.25 dB loss.
L
C
228/9.0
Allowance for 9 inches of Carrier Board trace
4.40 db loss
@ 0.28 dB /
GHz / inch and a 1.25 dB crosstalk allowance.
L
D
1.25 dB loss.
PCI Express Card Electromechanical Spec Rev 1.1 “guard
band” allowance for slot connector – includes 1.0 dB connector loss.
L
E
2.65 dB loss.
From PCI Express Card Electromechanical Spec., Rev.
1.1(without coupling caps; L
AR
). Implied crosstalk allowance is 1.25 dB.
Total
13.20 dB loss.
PCI Express Insertion Loss Budget, 2.5 GHz with Carrier Board Slot Card
For “device up” PCIe Gen 2 operation, the Module PCIe maximum trace length is restricted to 5.0 inches
and the Carrier Board maximum trace to 4.45 inches. Shorter lengths will yield additional margin and are
encouraged where possible. Results assumed FR4 dielectrics.
Other dielectrics with lower losses could be considered, but were not simulated
.
It can be noted that a use case exists that might result in reduced PCI Express bandwidth. This use case
is tied to Carrier boards with a PCI Express slot (device up). PCI Express Gen 1 and Gen 2 signaling
rates use the same PCI Express connector
– there is no mechanical keying mechanism to identify the
capabilities of the PCI Express slot or the PCI Express board plugged into the slot. This can lead to the
situation where the Module and PCI Express board attempt a PCI Express Gen2 signaling rate
connection over a Carrier that does not meet the routing guidelines for Gen 2 signaling rates. In a worst
case scenario the devices might connect at Gen2 signaling rate with a high number of errors impacting
the actual data throughput. It should be noted that there is a Carrier EEPROM which would allow the
Module to determine the Carrier Board capabilities but this is not a requirement in COM.0.
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