Advantech SOM-5991, Руководство пользователя

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59 SOM-5991 User Manual
Chapter 3
A
MI BIOS
3.2.3.5 IIO Configuration
Figure 3.37 IIO Configuration
 IIO PCIe Link on phase
Link training can be done either before memory chipset init or post chipset init.
 PCI Express Global Options:
– TX EQ WA
Use special table for TX_EQ and vendor specific cards.
– WA 4167453
Disable IIO VCP. Disable PCH VC1, set IIO CV1 & PCH VCP to TC2, clear
irp_misc_dfx0.force_no_snp_on_vc1_vcm.
– DMI Vc1 Control
Enable or Disable DMI Vc1.
– DMI Vcp Control
Enable or Disable DMI Vcp.
– DMI Vcm Control
Enable or Disable DMI Vcm.
– VC0 No-Snoop Configuration
Enable No-Snoop on reads and writes for Vc0 traffic.
– Gen3 Phase3 Loop Count
Change Loop Count as 1, 4, 16, or 256.
– Skip Phase3 Loop Count
Enable this option to avoid the system to be halted on DMI width/link degra-
dation.
– Power Halt on DMI Degradation
Power down unused ports.