Advantech SOM-5780, Руководство по конструкции

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Advantech SOM-Express Design Guide
Chapter 5 Carrier Board Design Guidelines 59
5.5 LVDS
5.5.1 Signal Description
Table 5-15 shows SOM-Express LVDS signals, including pin number, signals, I/0 and
descriptions.
Table 5-15 LVDS signals description
Pin Signal I/O Description
A71,73,75,78
A72,74,76,79 LVDS_A[0:3]+
LVDS_A[0:3]- O LVDS Channel A differential pairs
A81
A82 LV
LVDS_A_CK- O LVDS Channel A differential clock
B71,73,75,77
B72,74,76,78 LVDS_B[0:3]+
LVDS_B[0:3]- O LVDS Channel B differential pairs
B81
B82 LV
LVDS_B_CK- O LVDS Channel B differential clock
A77 LVDS_VDD_EN O LVDS panel power enable
B79 LVDS_BKLT_EN O LVDS panel backlight enable
B83 LVDS_BKLT_CTRL O LVDS panel backlight brightness control
A83 LVDS_I2C_CK O I2C clock output for LVDS display use
A84 LVDS_I2C_DAT O I2C data line for LVDS display use
5.5.2 Design Guideline
Figure 5-22 shows LVDS LCD connections.
Figure 5-22 LVDS LCD Connections
5.5.2.1 Package Length Constraints
Skew minimization requires chipset die-pad to LVDS connector trace length matching
of the LVDS signal pairs that belong to the same group including the clock strobe
signals of that group. The reason for this is to compensate for the package length
variation across each signal group in order to minimize timing variance. The chipset
does not equalize package lengths internally, SOM-Express compensates for the
mismatch length. Please be sure to be trace length matched on the carrier board.
Table LV-2 shows the LVDS Signals Trace Length Mismatch Mapping.
Each LVDS signal should be trace length matched to its associated clock strobe
within
±
10 mils. The Channel A clock strobe pair must also be trace length matched
to the Channel B clock strobe pair within
±
10 mils.