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Advantech SOM-Express Design Guide 

 

40 

Chapter 5  Carrier Board Design Guidelines

 

Chapter 5  Carrier Board Design Guidelines 

5.1 PCI-Bus 

SOM-Express provides a PCI Bus interface that is compliant with the PCI Local Bus 
Specification, Revision 2.3. The implementation is optimized for high-performance 
data streaming when SOM-Express is acting as either the target or the initiator on the 
PCI bus. For more information on the PCI Bus interface, please refer to the PCI Local 
Bus Specification, Revision 2.3. 

5.1.1 Signal Description 

Table 5-1 shows SOM-Express PCI bus signal, including pin number, signals, I/0, 
and descriptions. 

Table 5.1 PCI Signal Description 

Pin Signal 

I/O 

Description 

D50 

PCI_CLK 

O 

PCI 33 MHz clock output 

D48 PCI_CLKRUN# 

I/O 

Bidirectional pin used to support PCI clock run protocol for 
mobile systems 

C22,C19,
C17,D20 

PCI_REQ[0..3] I 

Bus Request signals for up to 4 external bus mastering PCI 
devices. When asserted, a PCI device is requesting PCI bus 
ownership from the arbiter. 

C20,C18,
C16,D19 

PCI_GNT[0..3] O 

Grant signals to PCI Masters. When asserted by the arbiter, the 
PCI master has been granted ownership of the PCI bus. 

- PCI_AD[0..31] 

I/O 

PCI Address and Data Bus Lines. These lines carry the address 
and data information for PCI transactions. 

D26,C33,
C38,C44 

PCI_C/BE[0..3] I/O 

PCI Bus Command and Byte Enables. Bus command and byte 
enables are multiplexed in these lines for address and data 
phases, respectively. 

D32 

PCI_PAR 

I/O 

Parity bit for the PCI bus. 

D33 PCI_SERR# 

I/O
OD 

System Error. Asserted for hardware error conditions such as 
parity errors detected in DRAM. 

C34 PCI_PERR# I/O 

Parity Error. For PCI operation per exception granted by PCI 2.1 
Specification. 

C15 

PME# 

I 

Power management event. 

C35 

PCI_LOCK# 
 

I/O 

Lock Resource Signal. This pin indicates that either the PCI 
master or the bridge intends to run exclusive transfers. 

C36 PCI_DEVSEL# 

I/O 

Device Select, active low. When the target device has decoded 
the address as its own cycle, it will assert DEVSEL#. 

D35 

PCI_TRDY# 
 

I/O 

Target Ready. This pin indicates that the target is ready to 
complete the current data phase of a transaction. 

C37 

PCI_IRDY# 
 

I/O 

Initiator Ready. This signal indicates that the initiator is ready to 
complete the current data phase of a transaction. 

D34 

PCI_STOP# 
 

I/O 

Stop. This signal indicates that the target is requesting that the 
master stop the current transaction. 

D36 

PCI_FRAME# 
 

I/O 

Cycle Frame of PCI Buses. This indicates the beginning and 
duration of a PCI access.  

C23 

PCI_RESET# 
 

I 

PCI Bus Reset. This is an output signal to reset the entire PCI 
Bus. This signal is asserted during system reset. 

C49,C50,
D46,D47 

PCI_IRQ[A…D] 

I 

PCI interrupt request lines. 

D49 PCI_M66EN I 

Module input signal indicates whether an off-module PCI device 
is capable of 66 MHz operation. Pulled to GND by Carrier Board 
device or by Slot Card if the devices are NOT capable of 66 
MHz operation.  
If the module is not capable of supporting 66 MHz PCI 
operation, this input may be a no-connect on the module.  
If the module is capable of supporting 66 MHz PCI operation, 
and if this input is held low by the Carrier Board, the module PCI 
interface shall operate at 33 MHz. 

Содержание SOM-5780

Страница 1: ...Advantech SOM Express System On Module Design Guide Version 1 1...

Страница 2: ...of their respective owners The product specifications design and this user s manuals content are subject to change without notice If you have any questions please contact your merchant or our service...

Страница 3: ...2 3 2 SOM 5782 Resources 22 Table 2 9 SOM 5782 IRQ Resources 22 Table 2 10 SOM 5782 DMA Resources 22 Table 2 11 SOM 5782 Memory Map 23 Table 2 12 SOM 5782 I O Map 24 Table 2 13 SOM 5782 Alternative De...

Страница 4: ...l Signals Impedance Requirement 39 4 3 Alternate Stack Ups 39 Chapter 5 Carrier Board Design Guidelines 40 5 1 PCI Bus 40 5 1 1 Signal Description 40 Table 5 1 PCI Signal Description 40 5 1 2 Design G...

Страница 5: ...ption 56 5 4 2 Design Guidelines 57 Figure 5 19 VGA Connections 57 5 4 3 Layout Guideline 57 Figure 5 20 VGA Layout Guidelines 57 Figure 5 21 RGB Output Layout Guidelines 58 5 5 LVDS 59 5 5 1 Signal D...

Страница 6: ...Signal Description 77 Table 5 23 PCIE Signal Description General purpose 77 Table 5 24 PEG Signal Description x16 Graphics 77 Table 5 25 Express Card Support 77 5 10 2 Design Guidelines 78 Figure 5 4...

Страница 7: ...press Module Receptacle 98 7 3 SOM Express Carrier Board Connector 98 Figure 7 3 SOM Express Carrier Board Plug 8mm Version 99 7 4 SOM Express Connector PCB Pattern 99 Figure 7 4 SOM Express Connector...

Страница 8: ...eat Sink 107 Figure 8 8 Heatsink Dimensions 107 Table 8 2 Chemistry Ingredient Temper Designation 108 8 8 4 Thermal Pad 108 Figure 8 8 Thermal Pad 108 Table 8 3 Thermal Pad 108 8 8 5 Screws109 Table 8...

Страница 9: ...of System on module FSB Front Side Bus synonymous with Host or CPU bus GMCH Refers to the Graphics Memory Controller Hub chipset component I2C Inter IC a two wire serial bus created by Philips ISA In...

Страница 10: ...ACPI Specification 3 0b http www acpi info spec htm COM Express Specification http www picmg org Ethernet IEEE 802 3 http www ieee org portal site I2C Bus Interface http www semiconductors philips com...

Страница 11: ...raditional customized CPU board development time and costs by as much as 80 2 1 Overview Advantech offers a wide range of SOM products to cater to each customer s demands The modular designs allow upg...

Страница 12: ...tors are finding an Advantech SOM solution already covers 80 of their feature requirements This makes SOM a powerful time and money saver SOM Customer Solution Board Your Customized Platform System On...

Страница 13: ...5780FL 00A1E Socket 478 Type SOM 5780FL S0A1E On board Intel Celeron M ULV 373 1 0G SOM 5780FL S4A1E On board Intel Pentium M LV 738 1 4G SOM 5780FL S8A1E With Intel Pentium M 745 1 8G SOM 5780FL U0A1...

Страница 14: ...n that fits a range of needs The Intel 915GM Express Chipset for Embedded Computing consisting of the Intel 915GM Graphic Memory Controller Hub GMCH and Intel I O Controller Hub 6 M ICH6 M is an optim...

Страница 15: ...t Intel 915GM GMCH ICH6 M Chipset 533 MHz FSB BIOS AWARD 4 Mbit Flash BIOS WatchDog Timer 255 levels timer interval from 1 to 255 sec or min setup by software jumperless selection generates system res...

Страница 16: ...Advantech SOM Express Design Guide 16 Chapter 2 SOM Express Overview 2 2 2 SOM 5782 Figure 2 2 SOM 5782 Block Diagram...

Страница 17: ...ystem Chipset Intel 945GM GMCH ICH7 M Chipset 533 MHz FSB BIOS AWARD 4 Mbit Flash BIOS 255 levels timer interval from 1 to 255 sec or min setup by software jumperless selection generates WatchDog Time...

Страница 18: ...IN CENTER LFE AC Link SIDESURR SURROUND SATA x 4 IT8888G PCI to ISA ISA SLOT 0 Mini PCI SLOT LPC Express Card Figure 2 3 SOM DB5700 Block Diagram SOM DB5700 Main Features Offers standard PC environmen...

Страница 19: ...8 ISA System CMOS real time clock 9 ISA Microsoft ACPI Compliant System Intel R 82801FBM SMBus Controller 24C3 10 11 12 ISA PS 2 Compatible Mouse 13 ISA Numeric data processor 14 ISA Primary IDE Chan...

Страница 20: ...FF0000 0DFFFFFF System board 0E000000 FEBFFFFF PCI bus D8000000 DFFFFFFF Intel R 82915GM Graphics Controller E0000000 E7FFFFFF Intel R 82915GM Graphics Controller E8000000 E807FFFF Intel R 82915GM Gra...

Страница 21: ...0000170 00000177 Secondary IDE Channel 000001F0 000001F7 Primary IDE Channel 00000274 00000277 ISAPNP Read Data Port 00000279 00000279 ISAPNP Read Data Port 000002F8 000002FF Communications Port COM2...

Страница 22: ...Bus Controller 27DA 12 ISA PS 2 Compatible Mouse 13 ISA Numeric data processor 14 ISA Primary IDE Channel 15 ISA Secondary IDE Channel 16 PCI Intel R 82801G ICH7 Family PCI Express Root Port 27D0 16 P...

Страница 23: ...7D0 0xFDA00000 0xFDAFFFFF Intel R 82801GR GH GHM ICH7 Family PCI Express Root Port 27E2 0xFDB00000 0xFDCFFFFF Intel R 82801GR GH GHM ICH7 Family PCI Express Root Port 27E2 0xFDB00000 0xFDCFFFFF Intel...

Страница 24: ...IDE Channel 0x01F0 0x01F7 Primary IDE Channel 0x0274 0x0277 ISAPNP Read Data Port 0x0279 0x0279 ISAPNP Read Data Port 0x02F8 0x02FF Communications Port COM2 0x0376 0x0376 Secondary IDE Channel 0x0378...

Страница 25: ...COM2 3F8 IRQ4 2F8 IRQ3 3E8 IRQ4 2E8 IRQ3 Disable LPT1 378 IRQ7 278 IRQ5 3BC IRQ7 Disable 2 4 PCI Routing Table 2 14 Advantech SOM Express Module PCI Routing SOM 5780 PCI Device IRQ REQ GNT IDSEL 82541...

Страница 26: ...0 5 V Vil Input Low Voltage 0 5 0 3Vcc V Vipu Input Pull up Voltage 0 7Vcc V 1 Voh Output High Voltage 0 9Vcc V Vol Output Low Voltage 0 1Vcc V 1 This specification should be guaranteed by design It i...

Страница 27: ...V Table 2 19 AC 97 CODEC analog I O DC specification Symbol Parameter Min Typ Max Unit Note AUXAL R Full scale input voltage 1 0 Vrms MIC Full scale input voltage 0 1 Vrms SNDL R Full scale output vol...

Страница 28: ...igh input threshold 1 5 2 0 V V High to Low input threshold 1 0 1 5 V 2 5 1 7 Ethernet Table 2 25 Ethernet I O Voltage Symbol Parameter Min Max Unit Note VIL Input Low Voltage 0 5 0 3Vcc V 1 VIH Input...

Страница 29: ...2 1 Vdd V VOL Output Low Voltage 0 4 V 1 System Management Bus SMBus Specification v2 0 2 Vdd is the voltage which the pull up resistor are connected 2 6 AC Specification 2 6 1 PCI Bus AC Spec Refer t...

Страница 30: ...chnology AT Attachment with Packet Interface 7 Volume 2 ATA ATAPI 7 V2 Annex B 5 for the details 2 6 6 I2C AC Spec Please refer to THE I 2C BUS SPECIFICATION VERSION 2 1 JANUARY 2000 for the DAC AC Ch...

Страница 31: ...escription Pin Types I Input O Output IO Bi Directional OD Open Drain Power Pin Types VCC2 5 2 5 V 5 Volts VCC3 3 3 V 5 Volts VSB3 3 3 V 5 Standby Power VCC3 5 3 3 V and 5 V tolerance GND System Groun...

Страница 32: ...SUS_S5 PSM O VSB3 A79 LVDS_A3 LVDS O A25 SATA2_RX SATA I AC on A80 GND FIXED PWR PWR A26 SATA2_RX SATA I AC on A81 LVDS_A_CK LVDS O A27 BATLOW PSM I VSB3 A82 LVDS_A_CK LVDS O A28 ATA_ACT SATA O VCC3...

Страница 33: ...B79 LVDS_BKLT_EN LVDS O VCC3 B25 SATA3_RX SATA I AC on B80 GND FIXED PWR PWR B26 SATA3_RX SATA I AC on B81 LVDS_B_CK LVDS O B27 WDT MISC O VCC3 B82 LVDS_B_CK LVDS O B28 AC_SDIN2 Audio I VSB3 B83 LVDS_...

Страница 34: ...PCI_AD2 PCI IO VCC3 5 C80 GND FIXED PWR PWR C26 PCI_AD4 PCI IO VCC3 5 C81 PEG_RX9 PCIE I AC off C27 PCI_AD6 PCI IO VCC3 5 C82 PEG_RX9 PCIE I AC off C28 PCI_AD8 PCI IO VCC3 5 C83 RSVD RSVD C29 PCI_AD10...

Страница 35: ...3 5 D80 GND FIXED PWR PWR D26 PCI_C BE0 PCI IO VCC3 5 D81 PEG_TX9 PCIE O AC on D27 PCI_AD9 PCI IO VCC3 5 D82 PEG_TX9 PCIE O AC on D28 PCI_AD11 PCI IO VCC3 5 D83 RSVD RSVD D29 PCI_AD13 PCI IO VCC3 5 D8...

Страница 36: ...jected to the fields created by changing current in neighboring traces Note the trace impedance target assumes that the trace is not subjected to the EMI fields created by changing current in neighbor...

Страница 37: ...m L1 Signal Layer Prepreg L2 Ground Layer Core L3 Power Layer Prepreg L4 Signal Layer Total Thickness 62 mils 62 mils Figure 4 1 Four Layer Stack up Table 4 1 Recommended Four Layer Stack Up Dimension...

Страница 38: ...r Total Thickness 62 mils 62 mils Core L3 IN1 Prepreg L4 IN2 L5 Power Layer Core Figure 4 2 Six Layer Stack up Table 4 2 Recommended Six Layer Stack Up Dimensions Layer Layer Single End Signals Differ...

Страница 39: ...rs choose to use different stack ups number of layers thickness trace width etc the following key elements should be observed 1 Final post lamination post etching and post plating dimensions should be...

Страница 40: ...s D33 PCI_SERR I O OD System Error Asserted for hardware error conditions such as parity errors detected in DRAM C34 PCI_PERR I O Parity Error For PCI operation per exception granted by PCI 2 1 Specif...

Страница 41: ...different SOM Express interrupt signal for each slot REQ Connected to a different SOM Express request signal for each slot if used GNT Connected to a different SOM Express grant signal for each slot i...

Страница 42: ...cted to the SOM Express INTA signal Please refer to 2 3 1 System Interrupt for more details 5 1 2 2 PCI Clock and Clock Skew The trace length for all PCI clocks should be matched and controlled PCI cl...

Страница 43: ...ors require four power rails 5 V 3 3 V 12 V and 12 V Systems that provide PCI connectors are required to provide all four rails in every system with the current budget Systems may optionally supply 3...

Страница 44: ...universal connector is used make sure the Vio jumper setting is correct when plugged into the riser card 2 Advantech s demo carrier board provides a 5 V connector and 5 V Vio for PCI slots Plugging a...

Страница 45: ...Device 1 PCI slot 2 or Device 2 PCI slot 3 or Device 3 PCI slot 4 or Device 4 PCI_CLK Clock Gen SOM Express SOM Express On Board Chipset W1 W2 W4 R1 R2 W5 Connector Clock Buffer Carrier board W3 Figur...

Страница 46: ...ICLK4 18 VSS 17 VC3B 16 VC5B 15 MS 1 33 MS1PCICLK PCIRST PCIREQ 1 STOP FRAME MS1PREQ 1 PCIGNT 1 MS1PREQ 3 MS1PGNT 2 MS1PREQ 2 33 MS1PGNT 3 MS1PGNT 1 33 33 PCICLK1 PCICLK2 PCICLK3 Figure 5 5 Design Exa...

Страница 47: ...ferential pairs channels 0 through 7 B44 USB_0_1_OC I USB over current sense USB channels 0 and 1 A pull up for this line shall be present on the module An open drain driver from a USB current monitor...

Страница 48: ...application needs more than two USB ports a low cost USB hub IC can be integrated onto the carrier board and connected to the USB0 or USB1 ports on the SOM Express module This provides a larger numbe...

Страница 49: ...the system The USBOC signal is used to signal overcurrent conditions to the system hardware and software Note that overcurrent protection typically allows relatively high currents to flow for brief pe...

Страница 50: ...on of Proper Routing Techniques 5 2 3 4 Stubs A very common routing mistake is shown in Figure 5 11 Here the designer could have avoided creating unnecessary stubs by proper placement of the pull down...

Страница 51: ...ignal is a 24 000 MHz serial data clock generated by SOM Express This signal has an integrated pull down resistor so that AC_BITCLK does not float when an Azalia codec or no codec is connected but the...

Страница 52: ...y Codec Tertiary Codec AC MC AMC AC MC AMC AC MC AMC SOM Express AC_RST AC_SDOUT AC_SYNC AC_BITCLK AC_SDIN 0 AC_SDIN 1 AC_SDIN 2 Figure 5 13 Azalia link Connections Note Azalia and AC 97 are mutually...

Страница 53: ...k panel microphone input signal should be independent routed and the ground return paths should be isolated from the carrier board ground plane Use a capacitor to filter noise from the microphone bias...

Страница 54: ...icient temperature coefficient and noise are not factors Located the crystal or oscillation close to the codec The AC link Azalia trace impedance from codec to SOM Express should be 55 15 5 3 3 2 EMI...

Страница 55: ...le 5 12 Azalia AC_SDOUT AC_SYNC AC_ BITCLK AC_RST Topology 1 Trace Impedance Azalia Requirements Trace length Series Termination Resistance Signal Length Matching 55 15 4 on 7 stripline 5 on 7 microst...

Страница 56: ...e the color of a dot or pixel on the monitor s screen 5 4 1 Signal Description Table 5 14 shows SOM Express VGA signals including pin number signals I 0 and descriptions Table 5 14 VGA signals descrip...

Страница 57: ...A_GRN VGA_BLU VGA_HSYNC VGA_VSYNC VGA_I2C_CK VGA_I2C_DAT Figure 5 19 VGA Connections 5 4 3 Layout Guideline 5 4 3 1 RLC Components The RGB outputs are current sources and therefore require 150 ohm loa...

Страница 58: ...ith no visible artifacts GNDRGB is an analog current balance path for the RGB lines In terms of layout GNDRGB should follow 2 traces that encapsulate the RGB traces all the way to the D shell connecto...

Страница 59: ...display use A84 LVDS_I2C_DAT O I2C data line for LVDS display use 5 5 2 Design Guideline Figure 5 22 shows LVDS LCD connections Figure 5 22 LVDS LCD Connections 5 5 2 1 Package Length Constraints Ske...

Страница 60: ...follows It is necessary to maintain the differential impedance Zdiff 100 15 where all traces are closely routed in the same area on the same layer Isolate all other signals from the LVDS signals to pr...

Страница 61: ...8 IDE_RESET O Low active hardware reset RSTISA inverted D77 IDE_CBLID O Input from off module hardware indicating the type of IDE cable being used High indicates a 40 pin cable used for legacy IDE mod...

Страница 62: ...s required it requires a special 80 conductor IDE cable for signal integrity For UDMA 66 support it is recommended the IDE bus and total cable length of carrier board do not exceed 13 inches Figure 5...

Страница 63: ...uting the IDE interface SOM Express provides one independent IDE channel This section provides guidelines for IDE connector cabling and carrier board design Additional external 0 resistors can be inco...

Страница 64: ...5 GBE0_LINK1000 OD Gigabit Ethernet Controller 0 1000 Mbit sec link indictor active low A14 GBE0_CTREF REF Reference voltage for Carrier board Ethernet channel 0 magnetics center tap The reference vol...

Страница 65: ...MDI 0 GBE0_MDI 1 GBE0_MDI 1 GBE0_MDI 2 GBE0_MDI 2 GBE0_MDI 3 GBE0_MDI 3 Figure 5 28 Gigabit Ethernet Connections 5 7 2 2 Power Considerations and Ethernet LED In general any section of traces that are...

Страница 66: ...race lengths of a differential pair equal to each other Do not use serpentines to try to match trace lengths in the differential pair Serpentines cause impedance variations causing signal reflections...

Страница 67: ...lose to the RJ 45 connector to limit EMI emissions Each differential pair of data signals is required to be parallel to each other with the same trace length on the component top layer and to be paral...

Страница 68: ...t be considered during the layout phase of an Ethernet controller These dimensions are identified in Figure 5 34 as A and B Distance A Transformer to RJ 45 Priority 1 The distance labeled A should be...

Страница 69: ...tion and with exactly the same lengths and physical dimensions for example width Distance B SOM Express to Transformer Priority 2 Distance B from Figure 5 34 should also be designed to extend as short...

Страница 70: ...t supports the following Composite video not used Component video Chrominance Pr analog signal S Video Chrominance analog signal 5 8 2 Design Guidelines 5 8 2 1 Termination resistor output filter and...

Страница 71: ...greater if possible in order to minimize crosstalk This is especially important for the TVDAC_B and TVDAC_C channels S video signals Figure 5 36 shows the TV DAC Video Filter Input FB C1 C2 TV DAC Fi...

Страница 72: ...onal external keyboard controller that can force a reset Pulled high on the module This is a legacy artifact of the PC AT A87 KBD_A20GATE I Input to module from optional external keyboard controller t...

Страница 73: ...module chipset and may result from a low SYS_RESET input a low PER_OK input a VCC_12V power input that falls below the minimum specification a watch dog timeout or may be initiated by the module soft...

Страница 74: ...s modules provide a software driven I2C port for communication with external I2C slave devices This port is implemented on SOM Express Pins I2C_DAT and I2C_CK 5 9 3 SMBus Most SOM Express modules prov...

Страница 75: ...rnal circuit asserts this signal it should be driven by an open drain driver and held low for a minimum of 15mS to initiate a reset Use of this input is optional The SOM Express module generates its o...

Страница 76: ...Advantech SOM Express Design Guide 76 Chapter 5 Carrier Board Design Guidelines SOM Express WDT Carrier board Power monitor MR Vcc Vcc Header Figure 5 42 Example of a watch dog circuit...

Страница 77: ...rential Transmit Pairs 16 through 31 These are same line as PEG_TX 0 15 and PCIE_RX 16 31 PCIE_RX 16 31 I PCI Express Differential Receive Pairs 16 through 31 These are same line as PEG_TX 0 15 and A8...

Страница 78: ...capacitor summary Table 5 26 PCI Express Capacitor Summary Type Value Tolerance Placement Length Matching Between Differential Pair AC Capacitor 75 nF 200 nF 20 Recommended to place close to the trans...

Страница 79: ...rom the SOM Express would connect to lane 0 of the device and lane 0 from the SOM Express would connect to lane 15 of the device Lane reversal need only be supported by one of the devices in the link...

Страница 80: ...y be left as No Connects Note Where x is the port number left as No Connect If no PCI Express ports will be implemented on the platform the PCIE _TX 0 5 and PCIE _RX 0 5 signals may be left as No Conn...

Страница 81: ...ize the total length of the traces in the pair throughout the trace each segment of trace length should be equal along the entire length of the pair Figure 5 47 shows an example LA must equal to LA LB...

Страница 82: ...5 mils Only 4 mil trace width on 8 mils spacing is allowed 100 20 Differential 5 10 3 3 PCI Express Topology 1 Device Down Routing Guidelines The device down topology allows a maximum of 15 inches fro...

Страница 83: ...topologies allow a maximum of 10 inches from SOM Express pin to the pin of the down device This maximum length takes into account all routing including the breakout region which should not exceed 0 2...

Страница 84: ...hannel 1 receive differential pair A22 A23 SATA2_TX SATA2_TX O Serial ATA or SAS Channel 2 transmit differential pair A25 A26 SATA2_RX SATA2_RX I Serial ATA or SAS Channel 2 receive differential pair...

Страница 85: ...ute all traces over continuous GND planes with no interruptions Avoid crossing over anti etched areas if at all possible Any discontinuity or split in the ground plane can cause signal reflections and...

Страница 86: ...e should be trace length matched The difference of two line traces in a TX or RX differential pair should be restricted to less than 20 mils but even less trace mismatch is encouraged Figure 5 53 show...

Страница 87: ...LPC_SERIRQ serialized IRQ is shared with the SIO 5 12 2 2 Signal Pull Up Requirements The LPC_AD 0 3 signals require pull up resistors to maintain their state during the turnaround TAR periods of a c...

Страница 88: ...erial Bus Connection frame ground Com port D Sub 9 6 8 5 1 7 2 3 4 9 bead bead bead bead bead bead bead bead 180p Super I O Transmitter Reciver SOM Express LPC_AD 0 LPC_AD 1 LPC_AD 2 LPC_AD 3 LPC_FRAM...

Страница 89: ...m digital circuitry analog circuitry and power and ground planes This isolation prevents noise sources located elsewhere on the PCB from corrupting susceptible circuits An example is power plane noise...

Страница 90: ...ces specifically designed for transient voltage suppression applications They have the advantage of a stable and fast time constant to avalanche and a stable clamping level after avalanche 3 LC filter...

Страница 91: ...te to Minimum Index Write Protect Read Data Track Diskette Change Motor on 0 Drive Select A Drive Density Select Head Select Drive Select B DIR Step Motor on 1 Write Data Write Enable SOM Express LPC_...

Страница 92: ...II 533 1GB 5VSB A 12V A Watts BIOS 1 min 0 31 2 42 30 59 XP IDLE 1 min 0 31 1 81 23 27 XP Standby S1 1 min 0 31 1 11 14 87 XP Standby S3 1 min 0 41 0 2 05 XP Run HCT 11 2 10 min 0 31 2 62 32 99 5VSB p...

Страница 93: ...25 54 XP IDLE 1 min 0 26 1 58 20 26 XP Standby S1 1 min 0 24 1 43 18 36 XP Standby S3 1 min 0 39 0 1 95 XP Run HCT 11 2 10 min 0 25 2 1 26 45 5VSB power 0 29 0 1 45 SOM 5782 A1011 CPU CPU L2400 1 66G...

Страница 94: ...XP Run HCT 11 2 10 min 0 29 2 11 26 77 5VSB power 0 24 0 1 2 Notes 1 Operates entirely from 12 Volt input power 2 To accommodate future modules it is recommended that the 12 V supply be capable of de...

Страница 95: ...idelines 6 2 1 ATX Power Delivery Block Diagram An ATX power source will provide 12 V 12 V 5 V 5 V 3 3 V 5 VSBY power if other voltage is required 3 3 VSBY LAN 2 5 on the carrier board an additional s...

Страница 96: ...AT Power Delivery Block Diagram An AT power source will provide 12 V and 5 V power An additional switching regulator or LDO will be required to simulate the ATX power 3 3 V There will be no standby vo...

Страница 97: ...ard An independent implementation specific set of holes and spacers shall be used to attach the heat spreader to the module Figure 7 1 shows the SOM Express module board mechanical dimensions The unit...

Страница 98: ...ti wicking solution applied that may help in processing with an aggressive flux The other versions of the parts may also be made available with this solution by the vendor The module connector is a re...

Страница 99: ...es of the 220 pin plug held by a carrier is AMP Tyco 3 5353652 6 0 5mm pitch Free Height 440 pin 8H Plug or equivalent Note the part number above shown with a leading 8 has an anti wicking solution ap...

Страница 100: ...top view of the receptacle looking into the receptacle as mounted on the backside of the module Figure 7 5 SOM Express Module Connector Pin Numbering 7 6 SOM Express Carrier Board Connector Pin Number...

Страница 101: ...copper which helps lead the heat away to the outer parts of the heatsink Keep in mind that a copper embedding is only useful if it is tightly bonded to the aluminium part for good thermal transfer Th...

Страница 102: ...aterial 8 4 Grounding Issues The mounting holes on all Advantech SOM Express are connected to digital circuit ground GND for improved EMC performance Using conductive screws and distance keepers will...

Страница 103: ...hermal solution for a module but provides a common interface between modules and implementation specific thermal solutions The overall module height from the bottom surface of the module board to the...

Страница 104: ...finish should have a maximum roughness average Ra of 1 6 m 63 in The critical dimension in Figure 8 3 is the module PCB bottom side to heat spreader top side This dimension shall be 13 00mm 0 65mm 0...

Страница 105: ...to a maximum height of 1mm dimension C in Figure 8 5 with the exception of the mating connectors Using Carrier Board topside components up to 1mm allows a gap of 0 2mm between Carrier Board module bo...

Страница 106: ...backplate and five mounting screw Active Heat Sink includes fan heat sink mounting clip thermal interface material retention mechanism backplate and five mounting screws CoolerMaster Part Number ECC 0...

Страница 107: ...Advantech SOM Express Design Guide Chapter 8 Heat Sink Recommended Design 107 Figure 8 7 SOM Express Heat Spreader Tolerances 8 8 3 Heat Sink Figure 8 8 Heatsink Dimensions...

Страница 108: ...on Rate 6063 T5 Over 15kgf x 7 Chemistry Ingredient Temper Designation Value Si Fe Cu Mn Cr Mg Zn Ti Flatness SPECIFIED 0 4258 0 2037 0 0032 0 0059 0 0028 0 5147 0 0000 0 00263 0 1mm 8 8 4 Thermal Pad...

Страница 109: ...Advantech SOM Express Design Guide Chapter 8 Heat Sink Recommended Design 109 8 8 5 Screws Table 8 4 Screws Specification Quantity M2 5 6 5 M2 5 16 5...

Страница 110: ...Advantech SOM Express Design Guide 110 Chapter 8 Heat Sink Recommended Design 8 8 6 Fan Figure 8 8 Fan...

Страница 111: ...Advantech SOM Express Design Guide Chapter 8 Heat Sink Recommended Design 111 Table 8 5 Fan Characteristics...

Страница 112: ...Advantech SOM Express Design Guide 112 Chapter 8 Heat Sink Recommended Design...

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