7
SOM-3567 User Manual
Chapter 1
G
eneral
Information
1.3.14.2
HD Audio Interface
Supports Intel HD Audio interface integrated in Intel Baytrail SoC.
1.3.14.3
LPC
Supports Low Pin Count (LPC) 1.1 specification, without DMA or bus mastering.
Allow to connect Super I/O, embedded controller, or TPM. LPC clock is 25MHz.
1.3.15
Serial Bus
1.3.15.1
SMBus
Supports SMBus 2.0 specification with Alert pin.
1.3.15.2
I2C Bus
Supports I2C bus 8-bit and 10-bit address modes, at both 100KHz and 400KHz.
1.3.16
I/O
1.3.16.1
Gigabit Ethernet
On-module Intel i210AT supports IEEE802.3 for 1000BASE-T, 100BASE-TX, and
10BASE-T (802.3, 802.3u, and 802.3ab). Supports IPv4, IPv6, TCP/UDP, SCTP,
ARP, Neighbor Discovery, EUI-64.
1.3.16.2
SATA
Supports 4 ports SATA Gen3 (6.0 Gb/s), backward compliant to SATA Gen2 (3.0 Gb/
s) and Gen1 (1.5 Gb/s). Maximum data rate is 600 MB/s. Supports AHCI 1.3.1 mode
(not support IDE mode).
1.3.16.3
USB3.0/USB2.0
1.
Supports 1 port USB3.0 Super Speed (SS, 5.0 Gbps) on xHCI.
2.
Supports 6 ports USB2.0 High Speed (HS, 480 Mbps) compliant to Full
Speed(FS) on either EHCI or xHCI controller.
1.3.16.4
SPI Bus
Supports BIOS flash only. SPI clock can be 50MHz, 33MHz, or 20MHz, capacity up
to 16MB.
1.3.16.5
GPIO
Qseven v2.1 defines GPIO as multi-function pins with the LPC Bus. Because the
LPC Bus can still used for various applications, we don’t do use the multiplex function
but provide the LPC Bus only.
However, we use Qseven v2.1 MFG_NC[3:0] reserve pins to implement 4 GPIO pins
for designs which still need it. If you have such inquiries please contact your FAE for
further help.
Qseven v2.1
USB3.0/2.0
USB2.0
HS P0 HS P1 HS P2 HS P3 HS P4 HS P5 HS P6 HS P7
USB3.0
SS P2
SS P0
SS P1
SOM-3567
SoC
HS P0 HS P1 HS P2
SS P0
Hub
HS P3 HS P4 HS P5
Qseven v2.1 USB OC# USB_0_1_OC# USB_2_3_OC# USB_4_5_OC# USB_6_7_OC#
SOM-3567 USB3.0
SS P0
USB2.0
HS P0 HS P1
HS P2 HS P3 -
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Содержание Qseven SOM-3567
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