Advantech PCIE-1203, Руководство пользователя

Страница: 11 / 24

5 PCIE-1203 User Manual
C
ha
pte
r 1
In
tro
du
ctio
n
Because synchronization between slaves in DC mode is done by internal clocks in
hardware, EtherCAT guarantee the time jitter is less than 1us.
Figure 1.5 EtherCAT Distributed Clock Jitter
1.1.1.5 Diagnosis with exact localization
EtherCAT is an ultra -fast I/O system. To reach the best high-speed communication,
high communication accuracy is demanded. EtherCAT comprises a wide range of
system-inherent diagnostic features which help detect and locate system errors pre -
cisely. Apart from broken wire detection and localization, the protocol, physical layer
and topology of the EtherCAT system enable individual quality monitoring of each
individual transmission segment.
As mentioned, every EtherCAT datagram ends with a 16 bit Working Counter (WKC)
to count the number of devices that were successfully addressed by this EtherCAT
datagram. Master can check the data exchange situation by WKC in the same cycle
and the error frame can be detected by analyzing the nodes’ error counters. The
slave application will be executed only as the frame is received correctly. The auto -
matic evaluation of the associated error counters enables precise localization of criti -
cal network sections.
Bit errors during transmission are detected reliably by the analysis of the CRC (Cyclic
Redundancy Check) check sum. CRC is an error-detecting code commonly used in
digital networks and storage devices to detect accidental changes to raw data. In
addition to the error detection and localization protocol, transmission physics and
topology of the EtherCAT system allow an individual quality monitoring of every sin -
gle transmission path. There is a very effective monitoring mechanism in EtherCAT.