Advantech PCI-1736UP, Руководство пользователя

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41 Appendix C
C.7 Interrupt Control Register — BASE+8H/CH/10H
The PCI-1736UP Interrupt Control Register controls the status of two
interrupt signal sources (IDI0, IDI1). The user can clear the interrupt by
writing its corresponding value to the
Interrupt Control Register , as
shown in below table.
IDI/nCLR Interrupt clear control bits ( n = 0 ~ 1)
This bit must first be cleared to service the next interrupt.
0 Don’t care
1 Clear the interrupt
IDInEN Interrupt enable control bits ( n = 0 ~ 1)
Read this bit to Enable/Disable the interrupt.
0 Disable
1 Enable
IDInRF Interrupt triggering control bits ( n = 0 ~ 1)
The interrupt can be triggered by a rising edge or falling edge of the inter-
rupt signal, as determined by the value in this bit.
0 Rising edge trigger
1 Falling edge trigger
Table C.6: Register for Interrupt Control
Write Interrupt Control Register
Bit # 7 6 5 4 3 2 1 0
BASE + 8H IDI1EN IDI0EN
BASE + CH IDI1RF IDI0RF
BASE + 10H IDI1CLR IDI0CLR