Advantech PCI-1736UP, Руководство пользователя

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PCI-1736UP User Manual 40
C.6 Interrupt Status Register — BASE+8H/CH/10H
The PCI-1736UP Interrupt Status Register control the status of two
interrupt signal sources (IDI0, IDI1).
IDInF Interrupt flag bits ( n = 0 ~ 1)
This bit is a flag indicating the status of an interrupt. User can read this bit
to get the status of the interrupt
0 No interrupt
1 Interrupt occurred
IDInEN Interrupt enable control bits ( n = 0 ~ 1)
Read this bit to Enable/Disable the interrupt.
0 Disable
1 Enable
IDInRF Interrupt triggering control bits ( n = 0 ~ 1)
The interrupt can be triggered by a rising edge or falling edge of the inter-
rupt signal, as determined by the value in this bit.
0 Rising edge trigger
1 Falling edge trigger
Table C.5: Register for Interrupt Status
Read Interrupt Status Register
Bit # 7 6 5 4 3 2 1 0
BASE + 8H IDI1EN IDI0EN
BASE + CH IDI1RF IDI0RF
BASE + 10H IDI1F IDI0F