Advantech MIC-3393, Руководство пользователя

Страница: 55 / 86

45 MIC-3393 User Manual
Chapter 2
A
MI BIOS
Setup
2.8.1 North Bridge Chipset Configuration
Figure 2.23 North Bridge chipset configuration
2.8.1.1 Hyper-Threading Function
Enable or disable Hyper-Threading functionality.
2.8.1.2 Crystal Beach / DMA
Enable or disable Crystal Beach / DMA configuration.
2.8.1.3 MCH Channel Mode
Select Channel Sequencing to allocate address channel - then 1. Select Channel
Interleave to interleave channel across channels. Select Single Channel 0 to force
single channel 0. The default setting is "Channel Interleave".
2.8.1.4 Patrol Scrubbing
Enable or disable ECC patrol scrub.
2.8.1.5 Demand Scrubbing
Enable or disable ECC demand scrub.
2.8.1.6 Channel Dependent Sparing
Enable or disable Channel-dependent rank/DIMM sparing.
2.8.1.7 Channel 0/1
Enable or disable Channel 0/1.
2.8.1.8 Channel Specific Sparing
Enable or disable rank/DIMM sparing feature of Channel 0/Channel 1.
2.8.1.9 Rank Interleaving
The default setting of Channel 0/Channel 1 is "4:1".
2.8.1.10 Dynamic Calibration
This feature allows for the memory interface to calibrate quickly by using the stored
calibration data from a previous power on. If enabled, CMOS must be cleared when
memory configuration changes.
2.8.1.11 Boots Graphic Adapter Priority
Select which graphics controller to use as the primary boot device. Two options are
available: "Auto" or "Onboard VGA". Select "Auto", the external graphics card will be
set as first priority. Select "Onboard VGA" to boot graphics from RTM only.
2.8.1.12 Read Completion Coalescing
The default setting of this item is "Auto".