Advantech MIC-3393, Руководство пользователя

Страница: 10 / 86

MIC-3393 User Manual x
Table 3.14:Serial modem device commands ............................. 55
Table 3.15: ................................................................................. 55
Table 3.16: ................................................................................. 55
Table 3.17: ................................................................................. 55
3.4 BMC Reset.............................................................................................. 56
Appendix A Pin Assignments ............................... 57
A.1 J1 Connector........................................................................................... 58
Table A.1: J1 CompactPCI I/O .................................................. 58
A.2 J2 Connector........................................................................................... 59
Table A.2: J2 CompactPCI I/O .................................................. 59
A.3 J3 Connector........................................................................................... 60
Table A.3: J3 CompactPCI I/O (LAN2/LAN3, 2.16) ................... 60
A.4 J5 Connector........................................................................................... 61
Table A.4: J5 CompactPCI I/O port ........................................... 61
A.5 Other Connectors.................................................................................... 62
Table A.5: CNSATA1 daughter board connector....................... 62
Table A.6: CNSATA1 daughter board connector....................... 62
A.5.1 M/D, PWR, BMC HB, and IDE/Hot-swap LEDs.......................... 62
Appendix B Programming the Watchdog Timer . 63
B.1 Watchdog Timer Programming Procedure ............................................. 64
Appendix C FPGA .................................................. 65
C.1 Features.................................................................................................. 66
C.2 FPGA I/O Registers ................................................................................ 66
Table C.1: LPC I/O registers address ........................................ 66
C.2.1 Debug Message.......................................................................... 66
Table C.2: Debug_Code [7:0] (LPC I/O address: 80H).............. 66
C.2.2 General Control and Status Registers ........................................ 67
C.2.3 General Purpose Registers ........................................................ 70
C.3 Watchdog Timer...................................................................................... 71
C.3.1 Initial Watchdog .......................................................................... 71
C.3.2 Program Watchdog..................................................................... 72
Appendix D Glossary ............................................. 73