Advantech IDK-1121WP Series, Руководство пользователя

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IDK-1121WP User Manual 18
POWER SEQUENCE
3.7 VLCD Power Dip Condition
1. Dip condition
3.5V
≤ VLCD< 4.5V, t
d
≤ 0ms
2. V
LCD
< 3.5V
V
LCD
-dip conditions should also follow the Power On/Off conditions for supply
voltage.
Note1! 1. The above power sequence should be satisfied at these case
– AC/DC Power On/Off
– Mode change ( resolution, frequency, timing, sleep mode, color
depth change, etc. )
If not to follow power sequence, there is a risk of abnormal display.
2. Please avoid floating state of interface signal at invalid period.
3. When the interface signal is invalid, be sure to pull down the power
supply for LCD VLCD to 0V.
4. The valid data must be complied with signal timing specifications
(Timing Table).
5. LED power must be turn on after power supply for LCD an interface
signal are valid.
6. If VLCD power is changed during on status, be sure to pull down
the LED power on to 0V.