Advantech 3718HG, Руководство пользователя

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Chapter 7 Programmable Pacer 51
The 8254 supports the counter latch operation in two ways. The first
way is to set bits RW1 and RW0 to 0. This setting latches the count of
the selected counter in a 16-bit hold register. The second way is to
perform a latch operation under the read-back command. Set bits SC1
and SC0 to 1 and CNT to 0. The latter method has the advantage of
operating several counters at the same time. A subsequent read
operation on the selected counter will retrieve the latched value.
7.5 Counter Applications
The 8254 programmable Interval timer/counter on your PCM-3718H/
3718HG interface module is a very useful device. You can program
counters 1 and 2 as pacers to generate A/D conversion trigger pulses.
Counter 0 is reserved for later module development.
Setting the Pacer Rate
The following equation gives the pacer rate:
Pacer rate = FCLK / (C1 *C2)
FCLK is either 1 MHz or 10 MHz, as set by jumper JP1. The follow-
ing steps tell you how to set the counter modes and constants:
1. Set Counter 1 to Mode 3 by writing ’76h’ to address BASE+15.
2. Set Counter 2’s divisor constant C1 by writing to BASE+13.
Constant C1 can be any 16-bit value from 2 to 65535. Because the
8254 has 8-bit registers, you should first write the low byte of C1 to
BASE+13, then write the high byte of C1 to BASE+13.
3. Set Counter 2 to Mode 3 by writing ‘B6h’ to address BASE+15.
4. Set Counter 2’s divisor constant C2 by writing to BASE+14.
Constant C2 can be any 16-bit value from 2 to 65535. Because the
8254 has 8-bit registers, you should first write the low byte of C2 to
BASE+14, then write the high byte of C2 to BASE+14.