LEC-iMX8M User’s Guide
SGET SMARC Rev 2.1
Page 23
copyright © 2021 ADLINK Technology Inc.
Name
Pin # Description
I/O Type
I/O
Level
Power
Domain
PU / PD
Comments
I2C_LCD_DAT
S140 DDC data line used for flat panel
detection and control
I/O OD
CMOS
1.8V
Runtime
PU 2k2
I2C_LCD_CK
S139 DDC clock line used for flat panel
detection and control
O OD
CMOS
1.8V
Runtime
PU 2k2
4.3.1.2
DSI mode (build option)
Name
Pin #
Description
I/O
Type
I/O
Level
Power
Domain
PU / PD
Comments
DSI0_D0-
DSI0_D1-
DSI0_D2-
DSI0_D3-
S125
S126
S128
S129
S131
S132
S137
S138
Primary DSI panel differential pair data lines
O LVDS
D-PHY
Runtime
Build option
D
DSI0_CLK-
S134
S135
Primary DSI panel differential pair clock lines.
O LVDS
D-PHY
Runtime
Build option
LCD0_VDD_EN
S133
Primary panel power enable, active high
O
CMOS
1.8V
Runtime
LCD0_BKLT_EN
S127
Primary panel backlight enable, active high
O
CMOS
1.8V
Runtime
LCD0_BKLT_PWM
S141
Primary panel brightness control through pulse width
modulation (PWM)
O
CMOS
1.8V
Runtime
DSI0_TE
S144
Primary DSI panel tearing effect sigal
I
CMOS
1.8V
Runtime
I2C_LCD_DAT
S140
DDC data line used for flat panel detection and
control
I/O OD
CMOS
1.8V
Runtime
PU 2k2
I2C_LCD_CK
S139
DDC clock line used for flat panel detection and
control
O OD
CMOS
1.8V
Runtime
PU 2k2
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