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Operation Theory

 39

 

Figure 4-16: Stop mode III

4.3 General Purpose Digital I/O

DAQ/PXI-2500 SERIES provides 24-line general-purpose digital I/
O (GPIO) through a 82C55A chip. 

The 24-line GPIO are separated into three ports: Port A, Port B
and Port C. High nibble (bit[7…4]), and low nibble (bit[3…0]) of
each port can be indi-vidually programmed to be either inputs or
outputs.  Upon system startup or reset, all the GPIO pins are reset
to high impedance inputs.

For more information on programmable I/O chip 82C55A, please
refer to http://www.intel.com.

Содержание NuDAQ-2500 Series

Страница 1: ...Advance Technologies Automate the World Manual Rev 2 01 Revision Date December 21 2006 Part No 50 12265 100 NuDAQ 2500 Series High Performance Analog Output Multi function Cards User s Manual...

Страница 2: ...or inability to use the product or documentation even if advised of the possibility of such damages This document contains proprietary information protected by copy right All rights are reserved No pa...

Страница 3: ...ice adlinktech com TEL 886 2 82265877 FAX 886 2 82265717 Address 9F No 166 Jian Yi Road Chungho City Taipei 235 Taiwan Please email or FAX this completed service form for prompt and satisfactory servi...

Страница 4: ......

Страница 5: ...r A Trig 5 System Synchronous Interface SSI 5 Calibration 5 Physical 5 Operating Environment 6 Storage Environment 6 1 4 Software Support 6 Programming Library 6 D2K LVIEW LabVIEW Driver 7 D2K OCX Act...

Страница 6: ...40 Timer Counter functions basics 40 General Purpose Timer Counter modes 41 4 5 Trigger Sources 45 Software Trigger 45 External Analog Trigger 45 4 6 Timing Signals 49 System Synchronization Interface...

Страница 7: ...Input Range and Converted Digital Codes 18 Table 4 3 Trigger Modes and Corresponding Trigger Sources 20 Table 4 4 Summary of Counters for Programmable Scan 20 Table 4 5 D A Output Versus Digital Code...

Страница 8: ...tive waveform generation w Post trigger 35 Figure 4 13 Infinite iterative waveform generation w Post trigger 36 Figure 4 14 Stop mode I 38 Figure 4 15 Stop mode II 38 Figure 4 16 Stop mode III 39 Figu...

Страница 9: ...PXI 2501 X Up to 4 analog input channels for DAQ PXI 2502 and 8 analog input channels for DAQ PXI 2501 X Programmable bipolar unipolar range for analog input chan nels and individual analog output ch...

Страница 10: ...libration X Build in programmable D A external reference voltage com pensator X Completely jumper less and software configurable 1 2 Applications X Automotive Testing X Arbitrary Waveform Generator X...

Страница 11: ...reference internal 10V or external up to 10V X Output range Z Bipolar 10V or external reference Z Unipolar 0 10V or 0 external reference X Settling time for 10 10V step 2 s X Slew rate 20V s X Output...

Страница 12: ...middle trigger and delay trigger X Data transfers Programmed I O and bus mastering DMA with scat ter gather X Input coupling DC X Offset error Z Before calibration 40mV max Z After calibration 1mV ma...

Страница 13: ...Slope Positive or negative software selectable X Hysteresis Programmable X Bandwidth 400khz X External Analog Trigger Input EXTATRIG X Impedance 40K X Coupling DC X Protection Continuous 35V maximum...

Страница 14: ...l demonstration purposes Please contact ADLINK dealers to purchase the formal license Programming Library For customers who are writing their own programs we provide function libraries for many differ...

Страница 15: ...the user s guide in the CD Manual Software Package DAQBench Evaluation English The above software drivers are shipped with the board Please refer to the Software Installation Guide in the package to...

Страница 16: ...8 Introduction...

Страница 17: ...or damaged contact the dealer from whom you purchased the product Save the shipping materi als and carton in case you want to ship or store the product in the future 2 2 Unpacking Your DAQ PXI 2500 SE...

Страница 18: ...s Press down on all the socketed IC s to make sure that they are properly seated Do this only with the module place on a firm flat surface Note DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED Yo...

Страница 19: ...Installation 11 2 3 DAQ PXI 2500 SERIES Layout Figure 2 1 PCB Layout of DAQ 2502 2501 Figure 2 2 PCB Layout of PXI 2502 2501...

Страница 20: ...sis for all PCI boards on your system Because configuration is con trolled by the system and software there is no jumper setting required for base address DMA and interrupt IRQ The configuration is su...

Страница 21: ...signals etc The pin assignments of the connectors are defined in the figures below AO_0 1 35 AGND AO_1 2 36 AGND AO_2 3 37 AGND AO_3 4 38 AGND AOEXTREF_A AI_0 5 39 AGND AI_1 6 40 AGND EXTATRIG AI_2 7...

Страница 22: ...F_B AI_3 AGND Input External reference for AO channel 4 7 AI input 3 9 12 AO_ 4 7 AI_ 4 7 AGND Output Input Voltage output of DA channel 4 7 AI channel 4 7 only for DAQ 2501 13 14 AO_TRIG_OUT_ A B DGN...

Страница 23: ...IO Programmable DIO of 8255 Port A 35 46 AGND Analog ground 47 48 EXTWFTRIG_ A B DGND Input External waveform trigger for AO channel 0 3 4 7 49 VCC DGND Power Output 5V Power Source 28 50 54 62 DGND D...

Страница 24: ...16 Signal Connections...

Страница 25: ...es of the DAQ PXI 2500 series are described in this chapter The functions include A D conversion D A conver sion Digital I O and General Purpose Counter Timer This oper ation theory will help you unde...

Страница 26: ...series AD Data Format The data format of the acquired 14 bit A D data is 2 s Complement coding Table 4 1 and 4 2 lists the valid input ranges and the ideal transfer characteristics Magnitude Bipolar I...

Страница 27: ...quire A D data at a precise and fixed rate A scan is a group of multiple channel samples and the scan interval is defined by the SI_counter Likewise the sample in terval of the multiple channels is de...

Страница 28: ...trigger occurs and it could be under Post Trigger or De lay Trigger mode Table 4 3 Trigger Modes and Corresponding Trigger Sources Counter Name Width Description Notes SI_counter 24 bit Scan Interval...

Страница 29: ...2500 series therefore the minimum setting of SI2_counter is 100 2 The Scan Interval can not be smaller than the interval of data Sampling Interval multiple by the Number of chan nels per Scan i e SI_c...

Страница 30: ...a length num ber_of_channels_enabled_for_scan_acquisition PSC_counter The Delay_counter clock source can be soft ware selected from Internal 40MHz Timebase external input AFI 1 or General Purpose Time...

Страница 31: ...Operation Theory 23 Figure 4 2 Post trigger Figure 4 3 Delay trigger...

Страница 32: ...to the host PC s memory with out CPU intervention The hardware temporarily stores the acquired data in the onboard Data FIFO buffer then transfers the data to the user defined DMA buffer in the host...

Страница 33: ...rag ment of memory blocks Users can configure the linked list for the input DMA channel and the output DMA channel individu ally Figure 4 5 shows the linked list that is constructed by three DMA de sc...

Страница 34: ...to 8 channel of 12 bit Digital to Analog Converter DAC available in the DAQ PXI 2502 Four D A channels are packed into one D A group i e DAQ PXI 2502 contains two D A groups and DAQ PXI 2501 has only...

Страница 35: ...es in Waveform Generation mode the waveform patterns are stored in FIFO with 8K maximum sam ples Waveform patterns larger than 8K are also supported by utilizing bus mastering DMA transfer supported b...

Страница 36: ...e options 10V or 3 3V However DA update timing trigger Source and trigger stop mode are all the same throughout that D A Group DAQ PXI 2500 SERIES provides the capability to fine tune the voltage refe...

Страница 37: ...able for applications that need to generate waveforms at a precise and fixed rate Various programmable counters will facilitate users to generate complex waveforms with great flexibility There are thr...

Страница 38: ...es the number of data in a wave form When value in UC_counter is smaller than the size of wave form pat terns the waveform is generated piece wisely IC_counter 16 bit Iteration Counts which defines ho...

Страница 39: ...st trigger generation when users want to generate waveform right after a trigger signal The number of patterns to be updated after the trigger signal is specified by UC_counter IC_counter as illustrat...

Страница 40: ...th respect to multiple incom ing trigger signals Users can set Trig_counter to specify the number of acceptable trigger signals Figure 4 11 illustrates an example Two waveforms are gener ated after th...

Страница 41: ...Operation Theory 33 Figure 4 9 Post Trigger Generation Figure 4 10 Delay Trigger Generation...

Страница 42: ...form generation If the size of a single waveform is smaller than that of the FIFO after initially loading the data from the host PC s memory the data in FIFO will be re used when a single waveform gen...

Страница 43: ...of waveform LUT say 32 the generated wave form will be a 2 cycle sine wave for every waveform period In conjunction with different trigger modes and counter setups users can manipulate a single wavef...

Страница 44: ...e next iteration of waveform generation will start as shown in Fig ure 4 2 3 If users are generating waveform piece wisely the next piece of waveform will be generated The DLY2_counter clock source ca...

Страница 45: ...t be a multiple of 4 Users can check WFG_in_progress waveform generation in progress status by software read back to confirm the stop of a waveform generation Stop Mode III After a mode III stop trigg...

Страница 46: ...38 Operation Theory Figure 4 14 Stop mode I Assuming the data in the data buffer are 2V 4V 2V 0V Figure 4 15 Stop mode II...

Страница 47: ...hip The 24 line GPIO are separated into three ports Port A Port B and Port C High nibble bit 7 4 and low nibble bit 3 0 of each port can be indi vidually programmed to be either inputs or outputs Upon...

Страница 48: ...inputs that can be controlled via hardware or software They are clock input GPTC_CLK gate input GPTC_GATE and up down control input GPTC_UPDOWN The GPTC_CLK input acts as a clock source to the timer c...

Страница 49: ...tware Current count value can be read back by software at any time GPTC_GATE is used to enable disable counting When GPTC_GATE is inactive the counter halts the current count value Figure 4 17 illustr...

Страница 50: ...counts the number of active edges on GPTC_CLK when GPTC_GATE is active GPTC_OUT outputs high and current count value can be read back via software after the completion of the pulse width measurement...

Страница 51: ...pulse width following an active GPTC_GATE edge These software programmable parame ters can be specified in terms of periods of the GPTC_CLK input Once the first GPTC_GATE edge triggers the single puls...

Страница 52: ...nter gener ates con tinuous periodic pulses with programmable pulse interval and pulse width following the first active edge of GPTC_GATE Once the first GPTC_GATE edge triggers the counter GPTC_GATE t...

Страница 53: ...tware Trigger This trigger mode does not need any external trigger source The trigger asserts right after users execute the specified function call A D and D A processes can receive an individual soft...

Страница 54: ...ditions Users can con figure the trigger conditions easily via software Below Low analog trigger condition Figure 4 26 shows the below low analog trigger condition the trigger signal asserts when the...

Страница 55: ...alog signal is higher than the High_Threshold voltage The Low_Threshold setting is not used in this trigger condition Figure 4 27 Above High analog trigger condition Inside Region analog trigger condi...

Страница 56: ...higher than the High_Threshold voltage where the hysteresis region is determined by the Low_Threshold voltage Figure 4 29 High Hysteresis analog trigger condition Low Hysteresis analog trigger condit...

Страница 57: ...bunch of counters and trigger signals in the FPGA on board There are 7 timing signals related to the DAQ timing which in turn influ ence the A D D A process and GPTC operation These sig nals are fed t...

Страница 58: ...xible connections between boards You can choose each of the 7 timing signals and which board to be the SSI master The SSI master can drive the timing signals of the slaves Users can thus achieve bette...

Страница 59: ...ference an ADC and a TrimDAC TrimDAC is a multi channel DAC that generates DC offsets that counteract the offsets from the main DACs Digital codes for the TrimDAC as well as the tem perature and the d...

Страница 60: ...constants in anyone of these user banks ADLink provides software for users to save calibration constants in an easy manner 5 3 Loading Calibration Constants Users can calibrate DAQ board in three sit...

Страница 61: ...sine wave trian gular wave saw wave ramp etc can be converted to Waveform LUT Using larger waveform means trading maxi mum output rate for lower harmonic distortion Arbitrary Function User defined arb...

Страница 62: ...ed applying sinusoidal voltage reference will result in an amplitude modulated AM waveform generation Users can use one D A chan nel to generate sine wave loop it back to AOEXTREF_A B pin and generate...

Страница 63: ...party products not manufactured by ADLINK will be covered by the original manufactur ers warranty X For products containing storage devices hard drives flash cards etc please back up your data before...

Страница 64: ...f battery fluid during or after change of batteries by customer user X Damage from improper repair by unauthorized ADLINK technicians X Products with altered and or damaged serial numbers are not enti...

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