ADLINK Technology LPCI-3488A Series, Руководство пользователя

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30 Operation Theory
3.2 Block Diagram
3.2.1 ADLINK GPIB Interface Cards Block Diagram
ADLINK’s LPCI-3488A and PXI-3488 GPIB interface cards include
a 2 KB FIFO inside the FPGA IP to maximize data transfer rates.
Its state-of-the-art state machine in the CPLD coordinates the data
flow between the PCI controller, FIFO and GPIB bus.
Figure 3-2: Block Diagram of ADLINK GPIB Interface Cards
The FIFO can buffer data from the master (either from the PCI
controller or external device) when the target is busy. Efficiency is
thus significantly improved when transferring large blocks of data.
FPGA
GPIB IP
(Built-in 2 KB FIFO)
PCI
Controller
Bus
Transceiver/
Receiver
CPLD