ADLINK Technology EOS-1200, Руководство пользователя

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System Description 23
EOS-1200
2.5 General Purpose Digital Signals
2.5.1 General Purpose Digital Output (EDO)
In the common ground connection of isolated digital output, as
shown, when a “1” (logic high) is written by FPGA to a DO chan-
nel, the sink current passes through the transistors and the DO
channel goes low. When a “0” (logic low) is written by FPGA to a
DO channel, no current passes through the transistors and the DO
channel goes high. When the load is of an “inductance nature”
such as a relay, coil or motor, the VDD pin must be connected to
an external power source. The extra connection is utilized for the
‘fly-wheel diode’ to form a current-release closed loop, so that the
transistors are protected from any high reverse voltage generated
by the inductance load when the output is switched from high to
low.
Do From
FPGA
Iso_+5V
EOS-1200
PC3H4
User Pull
High
Vdd
Clamp
DO
ISO_GND
User
Device
GND
User DI
User
Device
Load