16
System Requirements
Leading
EDGE COMPUTING
2.2
Module Power Up and Down
Issuing the PWR_EN signal powers the MXM module down, and
the system designer can decide whether to keep the module input
power when the MXM module is powered down.
Figure 2-2: Module Power Down
2.3
Reset Requirements
Figure 2-3: Reset Sequencing
Module
Input Power
PWR_EN
Module
Internal Power
PWR_GOOD
T
PVPERL
T
PERST-PG
T
PERST-CLK
T
FAIL
T
PVPERL
≥100 ms
T
PERST-CLK
≥100 μs
T
PERST-PG
≥200 μs
T
FAIL
≤ 500 ns
Module
Input Power
PWR_EN
PWR_GOOD
PEX_REFCLK
PEX_RST#
Содержание EGX-MXM-P2000
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