
62
Utilities
Offset 68H: WDT Lock Register
X
Bit 2 is used to choose the functionality of the timer. (0 =
Watchdog Timer mode, 1 = Free running mode) The free
running mode ignores the first stage and only uses Preload
Value 2. In free running mode it is not necessary to reload
the timer as it is done automatically every time the down
counter reaches zero.
X
Bit 1 enables or disables the WDT. (0 = Disabled, 1 =
Enabled)
X
Bit 0 will lock the values of this register until a hard reset
occurs or power is cycled. (0 = unlocked, 1 = locked) The
default is Unlocked.
GPIO Control Registers
There are three GPIOs on cPCI-6840 relate to watchdog timer.
They are listed as following. The GPIO control base port is 480H.
WDT_TOUT# pin selection
WDT_TOUT# signal is multiplexed with GPIO32. When using
WDT, this signal must be switched to WDT_TOUT# function. It
uses bit 0 of GP 30H to set WDT_TOUT function. (0
= WDT_TOUT#, 1 = GPIO32)
RESET hardware circuit selection
GPO24 of 6300ESB is designed to control reset circuit. When
GPO24 is low, system will reset according to the level of
WDT_TOUT# signal. When GPO24 is high, system will not be
reset by WDT_TOUT#. Set bit 24 of GP 04H to 0 for
output use. Bit 24 of GP 0CH determines the level of
GPO24. (0 = Low, 1 = High) There already exists a setting in
BIOS setup menu. (Integrated Peripherals page) User can set
this item before programming WDT.
WDT LED Control
GPO25 of 6300ESB is designed to control WDT LED. Two fea-
tures of WDT LED are supported on cPCI-6840. WDT LED
lights or blinks.
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