38
System Resources
Memory Range
Target
Dependency/Comments
FF40 0000h-FF4F FFFFh
FF00 0000h-FF0F FFFFh
LPC or SPI(or PCI)
Bit 0 in BIOS Decode Enable register is set
128 KB anywhere in 4GB
range
Integrated LAN
Controller
Enable using BAR in D25:F0(Integrated LAN Controller
MBARA)
4 KB anywhere in 4GB range
Integrated LAN
Controller
Enable using BAR in D25:F0(Integrated LAN Controller
MBARA)
1 KB anywhere in 4GB range
USB EHCI Controller
Enable using standard PCI mechanism(D29:F0)
64 KB anywhere in 4GB
range
USB xHCI Controller
Enable using standard PCI mechanism(D20:F0)
FED0 X000h-FED0 X3FFh
High Precision Event
Timers
BIOS determines the “fixed location which is one of
four,1-KB ranges where X(in the first column) is
0h,1h,2h,or 3h”
FED0 X000h-FED4 FFFFh
TPM on LPC
None
Memory Base/Limit anywhere
in 4 GB range
PCI Bridge
Enable using standard PCI mechanism(D30:F0)
Prefetchable Memory
Base/Limit anywhere in 64-bit
address range
PCI Bridge
Enable using standard PCI mechanism(D30:F0)
64 KB anywhere in 4 GB
range
LPC
LPC Generic Memory Range.Enable using setting
bit[0] of the LPC Generic Memory Range
register(D31:F0:offset 98h)
32 Bytes anywhere in 64-bit
address range
SMBus
Enable using standard PCI mechanism(D31:F3)
2 KB anywhere above 64 KB
to 4 GB range
SATA Host Controller #
1
AHCI memory-mapped registers.Enable using
standard PCI mechanism.(D31:F2)
Memory Base/Limit anywhere
in 4 GB range
PCI Express Root
Ports1-8
Enable using standard PCI mechanism(D28:F 0-7)
Prefetchable Memory
Base/Limit anywhere in 64-bit
address range
PCI Express Root
Ports1-8
Enable using standard PCI mechanism(D28:F 0-7)
4 KB anywhere in 64-bit
address range
Thermal Reporting
Enable using standard PCI mechanism(D34:F6
TBAR/TBARH)
4 KB anywhere in 64-bit
address range
Thermal Reporting
Enable using standard PCI mechanism(D34:F6
TBARB/TBARBH)
16 Bytes anywhere in 64-bit
address range
Intel(R) MEI #1,#2
Enable using standard PCI mechanism(D22:F 1:0)
4 KB anywhere in 4 GB range KT
Enable using standard PCI mechanism(D22:F3)
16 KB anywhere in 4 GB
range
Root Complex Register
Block(RCRB)
Enable using setting bit[0] of the Root Complex Base
Address register(D34:F0 offset F0h)