ADLINK Technology CM1-86DX2, Техническое руководство

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Using the Module 65
CM1-86DX2
4.7 I/O Address Map
The system chipset implements a number of registers in I/O address space. These registers
occupy the following map in the I/O space:
PCI Configuration Registers
DMA Control Registers
Instruction Counter Registers
Timer/Counter Registers
Table 4-4: PCI Configuration Registers
Address range (hex) Description
0CFB - 0CF8 PCI Configuration Address Register
0CFF – 0CFC PCI Configuration Data Register
Table 4-5: DMA Control Registers
Address range (hex) Description
0000 – 000F Slave DMA Control Registers
0081 – 008B DMA Page Registers
00C0 – 00DE Master DMA Controller Registers
0481 – 048B DMA High Page Registers
Table 4-6: Instruction Counter Registers
Address range (hex) Description
0493 – 0490 Instruction Counter Register
0497 – 0494 User Instruction Counter Register
0498 UIC Start Register
0499 UIC Stop Register
Table 4-7: Timer/Counter Registers
Address range (hex) Description
0040 Timer / Counter 0 Count Register
0041 Timer / Counter 1 Count Register
0042 Timer / Counter 2 Count Register
0043 Timer / Counter Control Register