ADC PG-PLUS PCS-718, Техническая практика

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Composite Clock Signals SCP-PCS718-010-06H
2 January 6, 2003 PCS-718 List 1
C
OMPOSITE
C
LOCK
S
IGNALS
Composite clock signals are a 64 kHz bipolar clock with 8 kHz bipolar violations, that define the bit and byte
boundaries of DDS data as it is transferred within a CO. In support of DDS interfaces, PG-Plus defines two
composite clock interfaces at the PAU/PMU card slot. The PAU/PMU selects the clock and translates it into bit
and byte clocks, which it then distributes to the COLUs. Wire-wrap pins on the backplane allow the composite
clock source to be terminated or daisy-chained to another shelf.
B
ACKPLANE
C
ONNECTIONS
Each shelf supports the connection of up to twelve COLUs or six FICOLUs, two PMX units, and one PAU or
PMU. The backplane of the PCS-718 List 1 contains the connectors shown in
Figure 2 and Table 1 . Wiring
external to the COT shelf should follow the provisions of the current edition of the National Electrical Code and
applicable local codes.
Figure 2. PCS-718 Shelf Backplane
Information in Tables 2 through 17 can be used for diagnostic and troubleshooting procedures under the
direction of an authorized ADC technical support representative.
P3
J4-J15
P2 J3 P1
TB1 J22 P5 J20 J2 HDSL pins J21
Test tip, ring &
EXT ACO pins
Composite
clock pins
Alarm relay
pins
J1