SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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6. Write 40H to Port 7, Bank Status/Select Register at Base
A 21CH to select register bank 1 where the event
polarity requirements of our application will be configured.
At this point, you are in Enhanced Mode Bank 1 where access
to the event polarity/status registers is obtained.
7. For change-of-state detection, both positive and negative
polarities must be sensed. As such, two channels are required
to detect a change-of-state on a single input signal. For our
example, IN00-IN03 will be used to detect positive events (low-
to-high transitions), IN04-IN07 will be used to detect negative
events (high-to-low transitions). Write 02H to the Port 6, Event
Polarity Control Register for Port 0-3 at Base A 218H
to set IN00-IN03 to positive edge detection, and IN04-IN07 to
negative edge detection.
Note that this port address has a dual function depending on
whether a read or write is being executed. As such, if the
current polarity configuration for the other ports must be
preserved, then it must be remembered since it cannot be read
back.
8. To enable event sensing for the port 0 input points, write FFH to
the Port 0, Event Sense Clear Register at Base A 200H
for input points in this bank.
Note that writing a 1 to a bit position enables the event sense
detector, while writing a 0 clears the event sensed without
enabling further event sensing.
9. Write 00H to the Port 7, Write Mask Register at Base A
21CH to select register bank 0 where the port 0 input channels
may be write-masked.
Note that the port 7 address bank selection only operates from
bits 6 & 7 of this register. Likewise, this register has a dual
function depending on whether a read or write is executed. As
such, the polarity settings cannot be read back and must be
remembered if they are to be preserved for successive writes.
At this point, you are in Enhanced Mode Bank 0 where access
to the write-mask register is obtained.
10. For our example, port 0 input points are to be used for inputs
only and writes to this port should be masked to prevent the
possibility of data contention between the built-in output
circuitry and the devices driving these inputs. Write 01H to the
Port 7, Write Mask Register at Base A 21CH to mask
writes to port 0.
11. Read 01H from the port 7, Write Mask Register at Base
A 21CH to verify bank 0 access (bits 6 & 7 are 0) and
port 0 write masking (bit 0 is 1).
12. (OPTIONAL) Write 01H to the Interrupt Enable Register (IER)
at Base A 23CH. Also, write 01H to the Interrupt
Register at Base A 000H to enable PMC470 control of
the Interrupt Request Line (INTA#).
When a change-of-state is detected, INTA# will be pulled low (if
the event sense detection circuitry has been enabled and IER bit
0=1). To enable further interrupts to occur for an event that has
already occurred for an I/O point, the Event Sense Status
Register must be written with a 1 to reenable event sensing for
subsequent events (but only after first writing 0 to the
corresponding bit position to clear the event sense flip/flop).
Note that the state of the inputs (on/off) can be determined by
reading the corresponding port address while in bank 0 of the
Enhanced Mode. However, the event sense status can only be
determined by reading the corresponding port address while in
bank 1 of the Enhanced Mode. Remember, the event sense
status is a flag that is raised when a specific positive or negative
transition has occurred for a given input point, while the state
refers to its current level.
4.0 THEORY OF OPERATION
This section provides a description of the basic functionality of
the circuitry used on the board. Refer to the Drawing 4501-870 as
you review this material.
PMC440 OPERATION
The PMC440 is built around a digital ASIC chip that provides
I/O interface and configuration functions. This chip performs
monitor and control functions of up to 48 open-drain outputs (only 32
are used by this model). The ASIC also provides debounce control
and event sensing functions.
A programmable logic device is installed on board to provide the
control interface necessary to operate the module. The Interrupt
Enable Register and Software Reset Control are also implemented
through the PLD.
Individual optocouplers for each channel provide isolation for the
PMC440. Channels are isolated from each other in groups of 8.
There are 8 channels to a group or port. Because the input lines of
a single port share a common connection, then individual inputs are
not isolated from each other within the same port. However,
separate port commons are provided to facilitate port-to-port
isolation.
Input optocouplers of this device are bipolar and accept voltages
in three ranges:
±
(4-18V),
±
(16-40V), and
±
(38-60V), DC or AC
peak. The optocouplers connect directly to a digital ASIC I/O
controller that provides the I/O read/write functionality, interrupt
handling, and debounce control.
PCI INTERFACE LOGIC
The PCI bus interface logic is imbedded within the FPGA. This
logic includes support for PCI commands, including: configuration
read/write, and memory read/write. In addition, the PCI target
interface performs parity error detection, uses a single 4K base
address register, and implements target abort, retry, and disconnect.
The PMC440 logic also implements interrupt requests via interrupt
line INTA#. J1 and J2 connectors also provide
±
12V and +5V to
power the module (
±
12V are not used).
A PCI bus read of the PMC module will initially terminate with a
retry. While the read data is moved to the read register (typically
1000ns), continued retries will result in retry terminations. The retry
termination allows the PCI bus to be free for other system
operations while the data is moved to the read register.
