SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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at the ASIC input. Note that the debounce time applies at the ASIC
input and does not include the optocoupler delay. You can combine
debounce with event sensing to obtain “glitch-free” edge detection of
incoming signals for all 32 channels. That is, the debounce circutry
will help filter out “glitches” or transients that can occur on received
signals, for error-free edge detection and increased noise immunity.
The debounce circuitry uses the 8MHz internal system clock to
derive the debounce times (see the Debounce Clock Select register
to enable the clock to be used). Debounce values of 3-4us, 48-
64us, 0.75-1ms, or 6-8ms may be selected (see the Debounce
Duration Register). As such, an incoming ASIC signal must be
stable for the debounce time before it is recognized as a valid input
or event.
Upon initialization of the debounce circuitry, be sure to delay at
least the programmed debounce time before reading any of the input
ports or event signals to ensure that the input data is valid prior to
being used by the software.
Interrupt Generation
This model provides control for generation of interrupts on
positive or negative events, for all 32 channels. Interrupts are only
generated in the Enhanced Mode for event channels when enabled
via the Event Sense/Status Register and when Bit 0 of the Interrupt
Enable Register is set to “1” at Base A 23CH. In addition,
bit-0 of the Interrupt Register at Base A 000H must be set
to logic “1”. Writing 0 to the corresponding event sense bit in the
Event Sense/Status Register will clear the event sense flip/flop.
Successive interrupts will only occur if the event channel has been
reset by writing a 1 to the corresponding event sense bit in the Event
Sense/Status Register (after writing 0 to clear the event sense
flip/flop). Interrupts may be reflected internally and reported by
polling the module, or optionally reported to the PCI bus by enabling
control of the Interrupt Request line (INTA#). Control of this line is
initiated via bit-0 of the Interrupt Enable Register (IER) and via bit-0
of the Interrupt Register.
Once INTA# goes active to signal an event it will stay active until
the conditions generating the interrupt have been cleared or returned
to normal. Also, the event sense bit must be cleared by writing a 0
to the required bit of the Event Sense Status Register. INTA# can
also be disabled by clearing bit-0 of the Interrupt Register at Base
A 000H.
Note that the state of the inputs (on/off) can be determined by
reading the corresponding port address while in bank 0 of the
Enhanced Mode. However, the event sense status can only be read
by reading the corresponding port address while in bank 1 of the
Enhanced Mode. Remember, the event sense status is a flag that is
raised when a specific positive or negative transition has occurred
for a given I/O point, while the state refers to its current level.
Note that the Interrupt Enable Register at Base A 23CH
is cleared following a power-up or bus initiated software reset. Also,
bit-0 of the Interrupt Register at Base A 000H is not
affected by a software reset. Keep this in mind when you wish to
preserve the information in this register following a reset.
Programming Example
The following example outlines the steps necessary to configure
the PMC440 for Enhanced Mode operation, to setup event-
generated interrupts, configure debounce, and read and write inputs.
It is assumed that the module has been reset and no prior (non-
default) configuration exists.
For this example, we will configure port 0 input points as a four-
channel change-of-state detector. For change-of-state detection,
both positive and negative polarities must be sensed and thus, two
channels are required to detect a change-of-state on a single input
signal. IN00-IN03 will be used to detect positive events (low-to-high
transitions), IN04-IN07 will be used to detect negative events (high-
to-low transitions). IN00 and IN04 will be tied to the first input
signal, IN01 & IN05 to the second, IN02 & IN06 to the third, and
IN03 & IN07 to the fourth. Any change-of-state detected on these
input signal lines will cause an interrupt to be generated.
1. After power-up or reset, the module is always placed in the
Standard Operating Mode. To switch to Enhanced Mode, you
must write four unique bytes to the Port 7, Enhanced Mode
Select Register at Base A 21CH, in consecutive order,
without doing any reads or writes to any other ports and with
interrupts disabled. The data pattern to be written is 07H first,
followed by 0DH, followed by 06H, then 12H.
At this point, you are in Enhanced Mode bank 0. Port 7 would
now be used to access register banks 1 & 2.
2. Write 80H to the Port 7, Bank Status/Select Register at Base
A 21CH to select register bank 2 where debounce will
be configured for our port 0 input channels.
At this point, you are in Enhanced Mode Bank 2 where access
to the debounce configuration registers is obtained.
3. We need to enable the 8MHz system clock to generate our
debounce time. By default, the debounce clock is not enabled.
Select the 8MHz system clock as the debounce clock by writing
01H to the Port 3, Debounce Clock Select Register at Base
A 20CH of this bank.
4. The default debounce duration is 3-4us with the 8MHz clock
enabled in step 3. This time applies to the ASIC input signal
and does not include optocoupler delay. Write 01H to the Port
1, Debounce Duration Register 0 at Base A 204H of
this bank to select a 48-64us debounce time. An incoming
signal must be stable for the entire debounce time before it will
be recognized as a valid input transition by the ASIC.
Note that Debounce Duration Register 1 (port address 2) would
be used to configure debounce durations for ports 4 & 5. Since
ports 4 & 5 are not used by this model, Debounce Duration
Register 1 has no effect.
5. Enable the debounce circuitry for port 0 inputs by setting bit 0 of
the Debounce Control Register. Write 01H to the Port 0,
Debounce Control Register at Base A 200H of this
bank.
If the module had been configured earlier, you would first read
this register to check the existing settings of debounce enable
for the other ports of this module with the intent of preserving
their configuration by adjusting the value written above.
