SERIES IP511 INDUSTRIAL I/O PACK ISOLATED QUAD EIA/TIA-422B COMMUNICATION MODULE
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Notes (Table 3.1):
1. The upper 8 bits of these registers are not driven. Pullups on the
carrier board data bus will cause these bits to always read high
(1’s).
2. The IP will not respond to addresses that are "Not Used".
3. All Reads and writes are 2 wait states (except ID PROM reads
which are 1 wait state).
4. Shaded registers apply only to the enhanced functionality of Model
IP511-64 and can be ignored for Model IP511-16. These registers
are accessed only after writing “BF” to the Line Control Register
(LCR).
This board operates in two different modes. In one mode, this
device remains software compatible with the industry standard 16C450
family of UARTS and provides double-buffering of data registers. In the
FIFO Mode (enabled via bit 0 of the FCR register), data registers are
FIFO-buffered so that read and write operations can be performed while
the UART is performing serial-to-parallel and parallel-to-serial
conversions. Two FIFO modes are possible: FIFO Interrupt Mode and
FIFO Polled Mode. Some registers operate differently between the
available modes and this is noted in the following paragraphs.
RBR - Receiver Buffer Register, Ports A-D (READ Only)
The Receiver Buffer Register (RBR) is a serial port input data
register that receives the input data from the receiver shift register and
holds from 5 to 8 bits of data, as specified by the character size
programmed in the Line Control Register (LCR bits 0 & 1). If less than
8 bits are transmitted, then data is right-justified to the LSB. If parity is
used, then LCR bit 3 (parity enable) and LCR bit 4 (type of parity) are
required. Status for the receiver is provided via the Line-Status
Register (LSR). When a full character is received (including parity and
stop bits), the data-received indication bit (bit 0) of the LSR is set to 1.
The host CPU then reads the Receiver Buffer Register, which resets
LSR bit 0 low. If the character is not read prior to a new character
transfer between the receiver shift register and the receiver buffer
register, the overrun-error status indication is set in LSR bit 1. If there
is a parity error, the error is indicated in LSR bit 2. If a stop bit is not
detected, a framing error indication is set in bit 3 of the LSR.
Serial asynchronous data is input to the receiver shift register via
the receive data line (RxD). From the idle state, this line is monitored
for a high-to-low transition (start bit). When the start bit is detected, a
counter is reset and counts the 16x clock to 7-1/2 (which is the center
of the start bit). The start bit is judged valid if RxD is still low at this
point. This is known as false start-bit detection. By verifying the start
bit in this manner, it helps to prevent the receiver from assembling an
invalid data character due to a low-going noise spike on RxD. If the
data on RxD is a symmetrical square wave, the center of the data cells
will occur within
±
3.125% of the actual center (providing an error margin
of 46.875%). Thus, the start bit can begin as much as one 16x clock
cycle prior to being detected.
Note that the port transceiver’s receiver is always enabled for this
model. Due to the isolation scheme employed, the first bit received
immediately after power-up may be initialized “high” and a data error
may be detected if the first bit was expected to be low. However,
subsequent bits will be received correctly.
THR - Transmitter Holding Register, Ports A-D (WRITE Only)
The Transmitter Holding Register (THR) is a serial port output data
register that holds from 5 to 8 bits of data, as specified by the character
size programmed in the Line Control Register. If less than 8 bits are
transmitted, then data is entered right-justified to the LSB. This data is
framed as required, then shifted to the transmit data line (TxD). In the
idle state, TxD is held high. In Loopback Mode, this data is looped back
into the Receiver Buffer Register.
Note that the port transceiver’s transmitter is always enabled for
this model. Due to the isolation scheme employed, sometimes the first
bit transmitted after power-up may be initialized “high” and a data error
may occur if the first bit was intended to be low. However, subsequent
bits will be transmitted correctly.
DLL & DLM - Divisor Latch Registers, Ports A-D (R/W)
The Divisor Latch Registers form the divisor used by the internal
baud-rate generator to divide the 8MHz system clock to produce an
internal sampling clock suitable for synchronization to the desired baud
rate. The output of the baud generator (RCLK) is sixteen times the
baud rate. Two 8-bit divisor latch registers per port are used to store
the divisors in 16-bit binary format. The DLL register stores the low-
order byte of the divisor, DLM stores the high-order byte. These
registers must be loaded during initialization.
Note that bit 7 of the LCR register must first be set high to access
the divisor latch registers (DLL & DLM) during a read/write operation.
Upon loading either latch, a 16-bit baud counter is immediately
loaded (this prevents long counts on initial load). The clock may be
divided by any divisor from 1 to 2
(16-1)
. The output frequency of the
baud rate generator (RCLK) is 16x the data rate. The relationship
between the output of the baud generator (RCLK), the baud rate, the
divisor, and the 8MHz system clock can be summarized in the following
equations:
DIVISOR = CLOCK FREQUENCY
÷
[BAUD RATE x 16];
RCLK = 16 x BAUD RATE;
= 16 x [CLOCK
÷
(16 x DIVISOR)] = CLOCK
÷
DIVISOR
The following table shows the correct divisor to use for generation
of some standard baud rates (based on the 8MHz clock). Note that
baud rates up to 512K may be configured. Provisions for installation of
an external crystal has been provided on the circuit board (16MHz).
With a 16MHz crystal, a 1Mbps baud rate is possible--you may contact
Acromag Applications Engineering to explore options in this area.
